Motorola MCF5281 用户手册

27-58

MOTOROLA

 

A change in the prescaler value while a conversion is in
progress is likely to corrupt the result. Therefore, any prescaler
write operation should be done only when both queues are in
the disabled modes.

To accommodate the wide range of the system clock frequency, QCLK is generated by a
programmable prescaler which divides the system clock. To allow the A/D conversion time
to be maximized across the spectrum of system clock frequencies, the QADC prescaler
permits the QCLK frequency to be software selectable. The frequency of QCLK is set with
the QPR field in QACR0.

The QADC periodic/interval timer can be used to generate trigger events at a
programmable interval, initiating execution of queue 1 and/or queue 2. The
periodic/interval timer stays reset under these conditions:

• Both queue 1 and queue 2 are programmed to any mode which does not use the 

periodic/interval timer.

• System reset is asserted.
• Stop mode is enabled.
• Debug mode is enabled.

ATD Converter

State Machine

2

7

2

8

2

9

2

10

2

11

2

12

2

13

2

14

2

15

2

16

2

17

Periodic Timer/Interval Timer

Select

Binary Counter

Queue 1 and Queue 2 Timer

Mode Rate Selection

Input Sample Time

from CCW

SAR

SAR Control

Periodic/Interval Trigger

Event for Q1 and Q2

Prescaler

System Clock

2

8

10

2

QPR[6:0]

Divide

by 2