Motorola MCF5281 用户手册
28-6
MCF5282 User’s Manual
MOTOROLA
Functional Description
28.5 Functional Description
28.5.1 Reset Sources
Table 28-5 defines the sources of reset and the signals driven by the reset controller.
To protect data integrity, a synchronous reset source is not acted upon by the reset control
logic until the end of the current bus cycle. Reset is then asserted on the next rising edge of
the system clock after the cycle is terminated. Whenever the reset control logic must
synchronize reset to the end of the bus cycle, the internal bus monitor is automatically
enabled regardless of the BME bit state in the chip configuration register (CCR). Then, if
the current bus cycle is not terminated normally the bus monitor terminates the cycle based
on the length of time programmed in the BMT field of the CCR.
logic until the end of the current bus cycle. Reset is then asserted on the next rising edge of
the system clock after the cycle is terminated. Whenever the reset control logic must
synchronize reset to the end of the bus cycle, the internal bus monitor is automatically
enabled regardless of the BME bit state in the chip configuration register (CCR). Then, if
the current bus cycle is not terminated normally the bus monitor terminates the cycle based
on the length of time programmed in the BMT field of the CCR.
Internal byte, word, or longword writes are guaranteed to complete without data corruption
when a synchronous reset occurs. External writes, including longword writes to 16-bit
ports, are also guaranteed to complete.
when a synchronous reset occurs. External writes, including longword writes to 16-bit
ports, are also guaranteed to complete.
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset
control logic does not wait for the current bus cycle to complete. Reset is asserted
immediately to the system.
control logic does not wait for the current bus cycle to complete. Reset is asserted
immediately to the system.
28.5.1.1 Power-On Reset
At power up, the reset controller asserts RSTO. RSTO continues to be asserted until V
DD
has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL
achieves phase lock. Then after approximately another 512 cycles, RSTO is negated and
the part begins operation.
achieves phase lock. Then after approximately another 512 cycles, RSTO is negated and
the part begins operation.
Table 28-5. Reset Source Summary
Source
Type
Power on
Asynchronous
External RSTI pin (not stop mode)
Synchronous
External RSTI pin (during stop mode)
Asynchronous
Watchdog timer
Synchronous
Loss of clock
Asynchronous
Loss of lock
Asynchronous
Software
Synchronous
LVD reset
Asynchronous