Motorola MCF5281 用户手册

29-10

MOTOROLA

 

Table 29-6 describes ABLR fields.

 

Table 29-7 describes ABHR fields.

The CSR defines the debug configuration for the processor and memory subsystem and
contains status information from the breakpoint logic. CSR is write-only from the
programming model. It can be read from and written to through the BDM port. CSR is
accessible in supervisor mode as debug control register 0x00 using the WDEBUG
instruction and through the BDM port using the 

RDMREG

 and 

WDMREG

 commands.

31–0

Address

Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. 
Breakpoints for specific addresses are programmed into ABLR.

31–0

Address

High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.

31

28

27

26

25

24

23

20

19

17

16

Field

BSTAT

FOF TRG HAL

T

BKPT

HRL

—

IPW

Reset

0000_0000_0000_0000

R/W

1

R

—

R/W

15

14

13

12

11

10

9

8

7

6

5

4

3

0

Field MAP TRC EMU

DDC

UHE

BTB

—

NPL

IPI

SSM

—

Reset

0000_0000_0000_0000

R/W R/W R/W R/W

R/W

R/W

R/W

R

R/W R/W R/W

—

DRc[4–0]

0000_0000_0000_0000