Motorola MCF5281 用户手册
2-8
MCF5282 User’s Manual
MOTOROLA
Programming Model
2.2.3.3
Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. To access the
vector table, the displacement of an exception vector is added to the value in VBR. The
lower 20 bits of the VBR are not implemented by ColdFire processors; they are assumed to
be zero, forcing the table to be aligned on a 1 MByte boundary.
vector table, the displacement of an exception vector is added to the value in VBR. The
lower 20 bits of the VBR are not implemented by ColdFire processors; they are assumed to
be zero, forcing the table to be aligned on a 1 MByte boundary.
2.2.3.4
Cache Control Register (CACR)
The CACR controls operation of the instruction/data cache memories. It includes bits for
enabling, freezing, and invalidating cache contents. It also includes bits for defining the
default cache mode and write-protect fields. The CACR is described in Section 4.4.2.1,
“Cache Control Register (CACR).”
enabling, freezing, and invalidating cache contents. It also includes bits for defining the
default cache mode and write-protect fields. The CACR is described in Section 4.4.2.1,
“Cache Control Register (CACR).”
2.2.3.5
Access Control Registers (ACR0, ACR1)
The access control registers, ACR0 and ACR1, define attributes for two user-defined
memory regions. These attributes include the definition of cache mode, write protect, and
buffer write enables. The ACRs are described in Section 4.4.2.2, “Access Control Registers
(ACR0, ACR1).”
memory regions. These attributes include the definition of cache mode, write protect, and
buffer write enables. The ACRs are described in Section 4.4.2.2, “Access Control Registers
(ACR0, ACR1).”
2.2.3.6
Memory Base Address Registers (RAMBAR, FLASHBAR)
Memory base address registers are used to specify the base address of the internal SRAM
and Flash modules and indicate the types of references mapped to each. Each base address
register includes a base address, write-protect bit, address space mask bits, and an enable
bit. For the MCF5282, FLASHBAR determines the base address of the on-chip Flash, and
RAMBAR determines the base address of the on-chip RAM. For more information, refer
to Section 5.3.1, “SRAM Base Address Register (RAMBAR)” and Section 6.3.2, “Flash
Base Address Register (FLASHBAR).”
and Flash modules and indicate the types of references mapped to each. Each base address
register includes a base address, write-protect bit, address space mask bits, and an enable
bit. For the MCF5282, FLASHBAR determines the base address of the on-chip Flash, and
RAMBAR determines the base address of the on-chip RAM. For more information, refer
to Section 5.3.1, “SRAM Base Address Register (RAMBAR)” and Section 6.3.2, “Flash
Base Address Register (FLASHBAR).”
2.3
Programming Model
Table 2-3 lists register names, the CPU space location, and whether the register is written
from the processor using the MOVEC instruction.
from the processor using the MOVEC instruction.
Table 2-3. ColdFire CPU Registers
Name
CPU Space (Rc)
Written with
MOVEC
Register Name
Memory Management Control Registers
CACR
0x002
Yes
Cache control register
ACR0, ACR1
0x004-0x005
Yes
Access control registers 0 and 1
Processor General-Purpose Registers