Motorola MCF5281 用户手册
2-12
MCF5282 User’s Manual
MOTOROLA
Exception Stack Frame Definition
All ColdFire processors inhibit interrupt sampling during the first instruction of all
exception handlers. This allows any handler to effectively disable interrupts, if necessary,
by raising the interrupt mask level contained in the status register. In addition, the V2 core
includes a new instruction (STLDSR) that stores the current interrupt mask level and loads
a value into the SR. This instruction is specifically intended for use as the first instruction
of an interrupt service routine which services multiple interrupt requests with different
interrupt levels. For more details see Section 2.14, “ColdFire Instruction Set Architecture
Enhancements.”
exception handlers. This allows any handler to effectively disable interrupts, if necessary,
by raising the interrupt mask level contained in the status register. In addition, the V2 core
includes a new instruction (STLDSR) that stores the current interrupt mask level and loads
a value into the SR. This instruction is specifically intended for use as the first instruction
of an interrupt service routine which services multiple interrupt requests with different
interrupt levels. For more details see Section 2.14, “ColdFire Instruction Set Architecture
Enhancements.”
2.6
Exception Stack Frame Definition
The exception stack frame is shown in Figure 2-7. The first longword of the exception stack
frame contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the
second longword contains the 32-bit program counter address.
frame contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the
second longword contains the 32-bit program counter address.
Figure 2-7. Exception Stack Frame Form
The 16-bit format/vector word contains 3 unique fields:
• A 4-bit format field at the top of the system stack is always written with a value of
4, 5, 6, or 7 by the processor indicating a two-longword frame format. See Table 2-6.
64–255
0x100–0x3FC
Next
User-defined interrupts
“Fault” refers to the PC of the instruction that caused the exception; “Next” refers to the PC
of the next instruction that follows the instruction that caused the fault.
Table 2-6. Format Field Encodings
Original SSP @ Time
of Exception, Bits 1:0
SSP @ 1st Instruction
of Handler
Format Field
00
Original SSP - 8
4
01
Original SSP - 9
5
10
Original SSP - 10
6
11
Original SSP - 11
7
Table 2-5. Exception Vector Assignments (continued)
Vector
Number(S)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
FORMAT
FS[3:2]
VECTOR[7:0]
FS[1:0]
STATUS REGISTER
PROGRAM COUNTER[31:0]
SSP
+ 0X4
31
17
15
0
27
25