Motorola MCF5281 用户手册
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2-28
MCF5282 User’s Manual
MOTOROLA
Branch Instruction Execution Times
NOTE
The execution times for moving the contents of the Racc,
Raccext[01,23], MACSR, or Rmask into a destination location
<ea>x shown in this table represent the best-case scenario
when the store instruction is executed and there are no load or
M{S}AC instructions in the EMAC execution pipeline. In
general, these store operations require only a single cycle for
execution, but if preceded immediately by a load, MAC, or
MSAC instruction, the depth of the EMAC pipeline is exposed
and the execution time is four cycles.
Raccext[01,23], MACSR, or Rmask into a destination location
<ea>x shown in this table represent the best-case scenario
when the store instruction is executed and there are no load or
M{S}AC instructions in the EMAC execution pipeline. In
general, these store operations require only a single cycle for
execution, but if preceded immediately by a load, MAC, or
MSAC instruction, the depth of the EMAC pipeline is exposed
and the execution time is four cycles.
2.13 Branch Instruction Execution Times
2.14 ColdFire Instruction Set Architecture
Enhancements
This section describes the new opcodes implemented as part of the Revision A+
enhancements to the basic ColdFire ISA.
enhancements to the basic ColdFire ISA.
Table 2-17. General Branch Instruction Execution Times
Opcode <EA>
Effective Address
Rn
(An)
(An)+
-(An)
(d16,An)
(d16,PC)
(d16,PC)
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
(d8,PC,Xi*SF)
xxx.wl
#xxx
bsr
—
—
—
—
3(0/1)
—
—
—
jmp
<ea>
—
3(0/0)
—
—
3(0/0)
4(0/0)
3(0/0)
—
jsr
<ea>
—
3(0/1)
—
—
3(0/1)
4(0/1)
3(0/1)
—
rte
—
—
10(2/0)
—
—
—
—
—
rts
—
—
5(1/0)
—
—
—
—
—
Table 2-18. BRA, Bcc Instruction Execution Times
Opcode
Forward
Taken
Forward
Not Taken
Backward
Taken
Backward
Not Taken
Not Taken
bra
2(0/0)
—
2(0/0)
—
bcc
3(0/0)
1(0/0)
2(0/0)
3(0/0)