Motorola MC68VZ328 用户手册
6-14
MC68VZ328 User’s Manual
Programming Model
CSD
Chip-Select Register D
0x(FF)FFF116
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
RO
SOP
ROP
UPSIZ
COMB
DRAM
FLASH
BSW
WS3–1
SIZ
EN
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
w
RESET
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0x0200
Table 6-10. Chip-Select Register D Description
Name Description
Setting
RO
Bit 15
Bit 15
Read-Only—This bit sets the chip-select to
read-only. Otherwise, read and write
accesses are allowed. A write to a read-only
area will generate a bus error if the BETEN bit
of the SCR is set. See Section 5.2.1, “System
Control Register,” on page 5-2 for more infor-
mation.
read-only. Otherwise, read and write
accesses are allowed. A write to a read-only
area will generate a bus error if the BETEN bit
of the SCR is set. See Section 5.2.1, “System
Control Register,” on page 5-2 for more infor-
mation.
0 = Read/write.
1 = Read-only.
1 = Read-only.
SOP
Bit 14
Bit 14
Supervisor-Use-Only Protected Memory
Block—This bit sets the protected memory
block to supervisor-only; otherwise, both
supervisor and user accesses are allowed.
Attempts to access the supervisor-only area
result in a bus error if the BETEN bit of the
SCR is set. See Section 5.2.1, “System Con-
trol Register,” on page 5-2 for more informa-
tion.
Block—This bit sets the protected memory
block to supervisor-only; otherwise, both
supervisor and user accesses are allowed.
Attempts to access the supervisor-only area
result in a bus error if the BETEN bit of the
SCR is set. See Section 5.2.1, “System Con-
trol Register,” on page 5-2 for more informa-
tion.
0 = Supervisor/user.
1 = Supervisor-only.
1 = Supervisor-only.
ROP
Bit 13
Bit 13
Read-Only for Protected Memory
Block—This bit sets the protected memory
block to read-only. Otherwise, read and write
accesses are allowed. If you write to a
read-only area, you will get a bus error.
Block—This bit sets the protected memory
block to read-only. Otherwise, read and write
accesses are allowed. If you write to a
read-only area, you will get a bus error.
0 = Read/write.
1 = Read-only.
1 = Read-only.
UPSIZ
Bits 12-11
Bits 12-11
Unprotected Memory Block Size—This field
determines the unprotected memory range of
the chip-select.
determines the unprotected memory range of
the chip-select.
00 = 32K.
01 = 64K.
10 = 128K.
11 = 256K.
01 = 64K.
10 = 128K.
11 = 256K.
COMB
Bit 10
Bit 10
Combining—This bit controls combining
RAS0 and RAS1 memory space to generate
RAS0. When this bit is set to 1, RAS1 can be
used as a general-purpose I/O signal.
RAS0 and RAS1 memory space to generate
RAS0. When this bit is set to 1, RAS1 can be
used as a general-purpose I/O signal.
0 = RAS0 to RAS0 memory space.
1 = RAS0 covers both RAS0 and RAS1 memory
1 = RAS0 covers both RAS0 and RAS1 memory
space B.
DRAM
Bit 9
Bit 9
DRAM Selection—This bit is used to enable
RAS and CAS signals. Configuring the CSC
register as a non-DRAM memory type
requires clearing the DRAM bit of the CSD
register.
RAS and CAS signals. Configuring the CSC
register as a non-DRAM memory type
requires clearing the DRAM bit of the CSD
register.
Note:
The DRAM bit overrides the flash bit.
0 = Select CSC[1:0] and CSD[1:0].
1 = Select CAS and RAS.
1 = Select CAS and RAS.