Motorola MC68VZ328 用户手册

6-16

In addition to the eight general-purpose chip-select signals, the MC68VZ328 has an emulation chip-select 
register (EMUCS) that is specifically designed for the in-circuit emulation module. This register provides 
wait states 12–0, depending on the type of chip used. External logic (DTACK) may also be used to have 
longer wait states. EMUCS is only valid for the 0xFFFC0000–0xFFFDFFFF memory location.

Emulation Chip-Select Register

The chip-select control register 1 (CSCTRL1) is one of three registers that provide features to control a 
wide variety of different memory types. The CSCTRL1 register provides supplemental memory-control 
features for chip-select logic. Control features include 16-bit SRAM support, extended size for unprotected 
memory space, and extended size for DRAM. See the following register display and Table 6-12 on 
page 6-17.

BIT 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BIT 

0

WS3–1

TYPE

rw

rw

rw

RESET

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0x0060

Reserved
Bits 15–7

Reserved 

These bits are reserved and should be set to 0.

WS3–1
Bits 6–4

Wait State—This field contains the 3 most 
significant bits of the 4-bit wait-state value. 
The least significant bit is located in the 
chip-select control register 1. The value of 
these 4 bits determines the number of wait 
states added to a bus cycle before an internal 
DTACK is asserted to terminate the 
chip-select cycle.

000 = 0 + WS0 wait states.
001 = 2 + WS0 wait states.
010 = 4 + WS0 wait states.
011 = 6 + WS0 wait states.
100 = 8 + WS0 wait states.
101 = 10 + WS0 wait states.
110 = 12 + WS0 wait states.
111 = External DTACK.

When using the external DTACK signal, you 
must select DTACK function in Port G.

WS0 is the EWS0 bit in the CSCTRL1 register.

Reserved
Bits 3–0

Reserved 

These bits are reserved and should be set to 0.