Motorola MC68VZ328 用户手册
7-14
MC68VZ328 User’s Manual
Programming Model
7.3.2
DRAM Control Register
The DRAM control (DRAMC) register is used to control the operation of the DRAM controller. The bit
position and values are shown in the following register display. The details about the register settings are
described in Table 7-7.
position and values are shown in the following register display. The details about the register settings are
described in Table 7-7.
DRAMC
DRAM Control Register
0x(FF)FFFC02
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
EN
RM
BC1–0
CLK
EDO
PGSZ
MSW
LSP
SLW
LPR
RST
DWE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0x0000
Table 7-7. DRAM Control Register Description
Name
Description
Setting
EN
Bit 15
Bit 15
Master DRAM Controller Enable—This bit
enables and disables the DRAM controller.
enables and disables the DRAM controller.
0 = Disable the DRAM controller.
1 = Enable the DRAM controller.
1 = Enable the DRAM controller.
RM
Bit 14
Bit 14
Refresh Mode—This bit sets the refresh mode.
0 = CAS-before-RAS refresh mode.
1 = Self-refresh mode.
BC1–0
Bit 13–12
Bit 13–12
Page Access Clock Cycle (Fast Page
Mode)—These bits determine the number of
additional clocks for the second and subsequent
accesses within a Fast Page Mode read cycle
after the first data word.
Mode)—These bits determine the number of
additional clocks for the second and subsequent
accesses within a Fast Page Mode read cycle
after the first data word.
1
00 = 1 additional clock (2 clocks/transfer).
01 = 2 additional clocks (3 clocks/transfer).
10 = 3 additional clocks (4 clocks/transfer).
11 = 4 additional clocks (5 clocks/transfer).
01 = 2 additional clocks (3 clocks/transfer).
10 = 3 additional clocks (4 clocks/transfer).
11 = 4 additional clocks (5 clocks/transfer).
CLK
Bit 11
Bit 11
Clock—This bit selects the clock that is provided
to the refresh timer.
to the refresh timer.
0 = CLK32 (Period A) is selected.
1 = System clock (Period B) is selected.
1 = System clock (Period B) is selected.
EDO
Bit 10
Bit 10
Extended Data Out—This bit selects the page
access mode for LCD DMA DRAM accesses.
This bit should only be set if the DRAM supports
EDO RAM transfers. When the EDO bit is set,
BC0 and BC1 do not affect the number of clocks
for LCD DMA DRAM accesses. EDO RAM mode
is the fastest LCD DMA transfer mode.
access mode for LCD DMA DRAM accesses.
This bit should only be set if the DRAM supports
EDO RAM transfers. When the EDO bit is set,
BC0 and BC1 do not affect the number of clocks
for LCD DMA DRAM accesses. EDO RAM mode
is the fastest LCD DMA transfer mode.
0 = Fast Page Mode mode is selected.
1 = EDO enables 1 clock for each LCD DMA data
1 = EDO enables 1 clock for each LCD DMA data
word transfer after the first word transfer.
Bits BC1–0 are ignored.
Bits BC1–0 are ignored.
PGSZ
Bits 9–8
Bits 9–8
Page Size—This field determines the page size
in the word for Fast Page Mode mode access.
in the word for Fast Page Mode mode access.
00 = 256
01 = 512
10 = 1,024
11 = 2,048
01 = 512
10 = 1,024
11 = 2,048
Reserved
Bits 7–6
Bits 7–6
Reserved
These bits are reserved and should be set to 0.
MSW
Bit 5
Bit 5
Slow Multiplexing—Setting this bit adds a sys-
tem clock for DRAM address multiplexing, which
allows for a heavily loaded A/DMA bus. Setting
this bit causes an additional wait state for all core
accesses and the first LCD DMA word access.
tem clock for DRAM address multiplexing, which
allows for a heavily loaded A/DMA bus. Setting
this bit causes an additional wait state for all core
accesses and the first LCD DMA word access.
0 = Normal address multiplexing.
1 = Slower address multiplexing.
1 = Slower address multiplexing.