Motorola MC68VZ328 用户手册
Programming Model
LCD Controller
8-21
8.3.19
Refresh Mode Control Register
Only a single bit in this register is used to enable or disable LCD self-refresh mode. The remaining bits are
reserved. The bit assignment for the register is shown in the following register display. The settings for the
bit in the register is listed in Table 8-19.
reserved. The bit assignment for the register is shown in the following register display. The settings for the
bit in the register is listed in Table 8-19.
RMCR
Refresh Mode Control Register
0x(FF)FFFA38
CCPEN
Bit 8
Bit 8
Contrast Control Enable—This bit is used to enable or dis-
able the contrast control function.
able the contrast control function.
0 = Contrast control is off.
1 = Contrast control is on.
1 = Contrast control is on.
PWx
Bits 7–0
Bits 7–0
Pulse Width 7–0—This bit controls the pulse-width of the
built-in pulse-width modulator, which controls the contrast of
the LCD screen. See Chapter 15, “Pulse-Width Modulator 1
and 2,” for more information.
built-in pulse-width modulator, which controls the contrast of
the LCD screen. See Chapter 15, “Pulse-Width Modulator 1
and 2,” for more information.
See description.
BIT 7
6
5
4
3
2
1
BIT 0
REF_ON
TYPE
rw
RESET
0
0
0
0
0
0
0
0
0x00
Table 8-19. Refresh Mode Control Register Description
Name
Description
Setting
REF_ON
Bit 7
Bit 7
Self-Refresh On—Setting this bit enables the self-refresh
mode of operation with the LCD panel.
mode of operation with the LCD panel.
0 = Disable self-refresh mode.
1 = Enter self-refresh mode.
1 = Enter self-refresh mode.
Reserved
Bits 6
Bits 6
–
0
Reserved
These bits are reserved and should
be set to 0.
be set to 0.
Note:
On entering self-refresh mode, the LSCLK and LD[7:0] signals stay low. FRM and LP work as normal.
Table 8-18. PWM Contrast Control Register Description (Continued)
Name
Description
Setting