Motorola MC68VZ328 用户手册
8-22
MC68VZ328 User’s Manual
Programming Example
8.3.20
DMA Control Register
The LCD controller contains an 8
×
16 pixel buffer, which stores DMA-in data from system memory. This
data is then passed to the LCD for display. When enough data has been removed from the buffer that it
needs to be refilled, a new DMA transfer must be initiated. The DMA control register controls when the
buffer should be refilled and the DMA burst length used when refilling. The bit assignments for the
register are shown in the following register display. The settings for the bits are listed in Table 8-20.
needs to be refilled, a new DMA transfer must be initiated. The DMA control register controls when the
buffer should be refilled and the DMA burst length used when refilling. The bit assignments for the
register are shown in the following register display. The settings for the bits are listed in Table 8-20.
DMACR
DMA Control Register
0x(FF)FFFA39
8.4
Programming Example
The following is an example of how to program the related registers to properly configure an LCD panel
with a resolution of 240
with a resolution of 240
×
160 pixels, 4 levels of grayscale, and a 4-bit LCD data interface. The virtual
image is 320 pixels wide and panned by 3 pixels.
Example 8-1. Programming Example
LCDINT
move.l #$A80000,#$FFFA00 ;display data address starts at $A80000
move.w #240,#$FFFA08
move.w #240,#$FFFA08
;LCD horizontal size is 240
move.w #159,#$FFFA0A
;LCD vertical size is 160
move.b #40,#$FFFA05
;4 level gray and 320 pixels wide image
move.b #$09,#$FFFA20
;LCD panel data bus is 4 bits,4 level gray
move.b #3,#$FFFA25
;pixel clock rate equal 1/4 of LCDCLK from PLL
move.b #10,#$FFFA29
;refresh rate adjustment
move.b #$03,#$FFFA2D
;shift picture by 3 pixels
move.b #$82,#$FFFA27
;switch on LCDC, 2 wait state for memory cycle
BIT 7
6
5
4
3
2
1
BIT 0
DMABL[3:0]
DMATM[2:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
RESET
0
1
1
0
0
0
1
0
0x62
Table 8-20. DMA Control Register Description
Name
Description
Setting
DMABL[3:0]
Bits 7
Bits 7
–
4
DMA Burst Length—This field sets the number of words to be
loaded to the pixel buffer in each DMA cycle.
loaded to the pixel buffer in each DMA cycle.
See description and table
footnote.
footnote.
Reserved
Bit 3
Bit 3
Reserved
This bit is reserved and
should be set to 0.
should be set to 0.
DMATM[2:0]
Bits 2
Bits 2
–
0
DMA Trigger Mark—This field sets the low-level mark in the pixel
buffer to trigger a DMA request. The low-level mark equals to the
number of words left in the pixel buffer.
buffer to trigger a DMA request. The low-level mark equals to the
number of words left in the pixel buffer.
See description and table
footnote.
footnote.
Note:
Since the FIFO size is 8
×
16, DMABL and DMATM must be programmed based on the following criteria:
F_HI + F_LO <= 8
1 <= F_HI <= 8
1<= F_LO <= 6
1 <= F_HI <= 8
1<= F_LO <= 6