Motorola MC68VZ328 用户手册
Modules of the MC68VZ328
Introduction
1-9
and sleep. When in sleep mode, the CGM wakes up automatically when any unmasked external or internal
interrupt occurs. See Chapter 4, “Clock Generation Module and Power Control Module,” for more detailed
information.
interrupt occurs. See Chapter 4, “Clock Generation Module and Power Control Module,” for more detailed
information.
1.3.3
System Control
The primary function of the system control module is to provide configuration control of several other
modules in the DragonBall VZ. These registers grant permission for access to many of the internal
peripheral registers. In addition, the module controls address space of the internal peripheral registers and
the bus time-out control and status (bus error generator). System control also is used to program the drive
current of the GPIO lines. See Chapter 5, “System Control,” for more information.
modules in the DragonBall VZ. These registers grant permission for access to many of the internal
peripheral registers. In addition, the module controls address space of the internal peripheral registers and
the bus time-out control and status (bus error generator). System control also is used to program the drive
current of the GPIO lines. See Chapter 5, “System Control,” for more information.
1.3.4
Chip-Select Logic
The MC68VZ328 provides eight programmable general-purpose chip-select signals to allow the selection
of a wide variety of memory or external peripherals. Each chip-select signal provides a write-protect
option, internal and external DTACK generation, and 8-bit and 16-bit data port size selection. For more
detailed information about using the chip-select logic, see Chapter 6, “Chip-Select Logic.”
of a wide variety of memory or external peripherals. Each chip-select signal provides a write-protect
option, internal and external DTACK generation, and 8-bit and 16-bit data port size selection. For more
detailed information about using the chip-select logic, see Chapter 6, “Chip-Select Logic.”
1.3.5
DRAM Controller
The DRAM controller provides a glueless interface for either 8-bit or 16-bit DRAM. It supports EDO
RAM, Fast Page Mode, and synchronous DRAM. The DRAM controller provides row address strobe
(RAS) and column address strobe (CAS) signals for up to a maximum of two banks of DRAM. In addition
to controlling DRAM, the DRAM controller supports access for LCD controller burst accesses. See
Chapter 7, “DRAM Controller,” for more information about this module.
RAM, Fast Page Mode, and synchronous DRAM. The DRAM controller provides row address strobe
(RAS) and column address strobe (CAS) signals for up to a maximum of two banks of DRAM. In addition
to controlling DRAM, the DRAM controller supports access for LCD controller burst accesses. See
Chapter 7, “DRAM Controller,” for more information about this module.
1.3.6
LCD Controller
The LCD controller provides display data for external LCD drivers or for an LCD panel. The LCD
controller fetches display data directly from system memory through periodic DMA transfer cycles. For
this reason, an understanding of the DRAM controller is recommended. For more information, please refer
to Chapter 7, “DRAM Controller,” as well as Chapter 8, “LCD Controller.”
controller fetches display data directly from system memory through periodic DMA transfer cycles. For
this reason, an understanding of the DRAM controller is recommended. For more information, please refer
to Chapter 7, “DRAM Controller,” as well as Chapter 8, “LCD Controller.”
1.3.7
Interrupt Controller
The interrupt controller prioritizes internal and external interrupt requests and generates a vector number
during the CPU interrupt-acknowledge cycle. Interrupt nesting is also provided so that an interrupt service
routine of a lower-priority interrupt may be suspended by a higher-priority interrupt request. The on-chip
interrupt controller features prioritized interrupts, a fully nested interrupt environment, programmable
vector generation, and unique vector number generation for each interrupt level. For additional information
about this module, see Chapter 9, “Interrupt Controller.”
during the CPU interrupt-acknowledge cycle. Interrupt nesting is also provided so that an interrupt service
routine of a lower-priority interrupt may be suspended by a higher-priority interrupt request. The on-chip
interrupt controller features prioritized interrupts, a fully nested interrupt environment, programmable
vector generation, and unique vector number generation for each interrupt level. For additional information
about this module, see Chapter 9, “Interrupt Controller.”