Motorola MC68VZ328 用户手册
Chip-Select Operation
Chip-Select Logic
6-3
chip-select–controlled area can be programmed as read/write, which provides optimal memory use, as
shown in Figure 6-1. This area can be defined by programming the UPSIZ bits in the CSB, CSC, and CSD
registers to between 32K and the entire chip-select area.
shown in Figure 6-1. This area can be defined by programming the UPSIZ bits in the CSB, CSC, and CSD
registers to between 32K and the entire chip-select area.
Figure 6-1. Size Selection and Memory Protection for CSB0 and CSB1
6.2.2
Programmable Data Bus Size
Each chip-select can be configured to address an 8- or 16-bit space. Both 16- and 8-bit contiguous address
memory devices can be mixed on a 16-bit data bus system. If the CPU performs a 16-bit data transfer in an
8-bit memory space, then two 8-bit cycles will occur. However, the address and data strobes remain
asserted until the end of the second 8-bit cycle. In this case, only the external CPU data bus upper byte
(D[15:8]) is used, and the least significant bit of the address (A0) increments automatically from one to the
next. A0 should be ignored in 16-bit data bus cycles even if only the upper or lower byte is being read or
written. For an external peripheral that only needs an 8-bit data bus interface and does not require
contiguous address locations (unused bytes on empty addresses), use a chip-select configured to a 16-bit
data bus width and connect to the D[7:0] pins. This balances the load of the two data bus halves in an 8-bit
system. The internal data bus is 16 bits wide. All internal registers can be read or written in a zero
wait-state cycle.
memory devices can be mixed on a 16-bit data bus system. If the CPU performs a 16-bit data transfer in an
8-bit memory space, then two 8-bit cycles will occur. However, the address and data strobes remain
asserted until the end of the second 8-bit cycle. In this case, only the external CPU data bus upper byte
(D[15:8]) is used, and the least significant bit of the address (A0) increments automatically from one to the
next. A0 should be ignored in 16-bit data bus cycles even if only the upper or lower byte is being read or
written. For an external peripheral that only needs an 8-bit data bus interface and does not require
contiguous address locations (unused bytes on empty addresses), use a chip-select configured to a 16-bit
data bus width and connect to the D[7:0] pins. This balances the load of the two data bus halves in an 8-bit
system. The internal data bus is 16 bits wide. All internal registers can be read or written in a zero
wait-state cycle.
Except for CSA0 and EMUCS, all chip-select signals are disabled by default. The data bus width (BSW)
field of the chip-select option register enables 16- and 8-bit data bus widths for each of the 16 chip-select
ranges. The initial bus width for the boot chip-select can be selected by placing a logic 0 or 1 on the BUSW
pin at reset to specify the width of the data bus. This allows a boot EPROM of the data bus width to be used
in any given system. All external accesses that do not match one of the chip-select address ranges are
assumed to be a 16-bit device. This results in a single access performed for a 16-bit transfer. If it is applied
to an 8-bit port, the port is accessed every other byte.
field of the chip-select option register enables 16- and 8-bit data bus widths for each of the 16 chip-select
ranges. The initial bus width for the boot chip-select can be selected by placing a logic 0 or 1 on the BUSW
pin at reset to specify the width of the data bus. This allows a boot EPROM of the data bus width to be used
in any given system. All external accesses that do not match one of the chip-select address ranges are
assumed to be a 16-bit device. This results in a single access performed for a 16-bit transfer. If it is applied
to an 8-bit port, the port is accessed every other byte.
The boot chip-select is initialized from reset to assert in response to any address except the on-chip register
space (0xFFFFF000 to 0xFFFFFFFF). This ensures that a chip-select to the boot ROM or EPROM will
fetch the reset vector and execute the initialization code, which should set up the chip-select ranges.
space (0xFFFFF000 to 0xFFFFFFFF). This ensures that a chip-select to the boot ROM or EPROM will
fetch the reset vector and execute the initialization code, which should set up the chip-select ranges.
A logic 0 on the BUSW pin sets the boot device’s data bus to be 8 bits wide, and a logic 1 sets it to be 16
bits wide. At reset, the data bus port size for CSA0 and the data width of the boot ROM device are
determined by the state of BUSW. The other chip-selects are initialized to be nonvalid, so they will not
assert until they are programmed and the EN bit is set in the chip-select registers.
bits wide. At reset, the data bus port size for CSA0 and the data width of the boot ROM device are
determined by the state of BUSW. The other chip-selects are initialized to be nonvalid, so they will not
assert until they are programmed and the EN bit is set in the chip-select registers.
CSB0
CSB1
Up to 16 Mbyte
RAM
Memory
Map
Up to 16 Mbyte
Up to 4 Mbyte
(Supervisor-Only, Read-Only)
Unprotected Memory (Read/Write)
Protected Memory