Motorola MVME2300 Series 用户手册
3-1
3
3
Falcon ECC Memory Controller
Chip Set
Introduction
The Falcon DRAM controller ASIC is designed for the MVME2300
family of boards. It is used in sets of two to provide the interface between
the PowerPC 60x bus (also called MPC60x bus or MPC bus) and a 144-bit
ECC-DRAM memory system. It also provides an interface to ROM/Flash.
family of boards. It is used in sets of two to provide the interface between
the PowerPC 60x bus (also called MPC60x bus or MPC bus) and a 144-bit
ECC-DRAM memory system. It also provides an interface to ROM/Flash.
This chapter provides a functional description and programming model for
the Falcon chip set. Most of the information necessary to use the device in
a system, program it in a system, and test it can be found here.
the Falcon chip set. Most of the information necessary to use the device in
a system, program it in a system, and test it can be found here.
Features
The following table summarizes the characteristics of the Falcon chip set.
Table 3-1. Features of the Falcon Chip Set
Function
Features
DRAM Interface
Double-bit error detect/Single-bit error correct on 72-bit basis
Up to four blocks
Programmable base address for each block
Two-way interleave factor
Built-in Refresh/Scrub
Error Notification for
DRAM
DRAM
Software-programmable Interrupt on Single/Double-Bit error
Error address and Syndrome Log Registers for Error Logging
Does not provide TEA_ on Double-Bit Error. (Chip has no TEA_ pin.)
ROM/Flash Interface
Two blocks with two 8-bit devices, or two 32-bit devices per block