Motorola MVME2300 Series 用户手册

Raven Interrupt Controller

http://www.motorola.com/computer/literature

2-91

The hardware and software overhead required to update the Task Priority 
register synchronously with instruction execution may far outweigh the 
anticipated benefits of the Task Priority register. To minimize this 
overhead, the interrupt controller architecture should allow the Task 
Priority register to be updated asynchronously with respect to instruction 
execution. Lower-priority interrupts may continue to occur for an 
indeterminate number of cycles after the processor has updated the Task 
Priority register. If this is not acceptable, the interrupt controller 
architecture should recommend that if the Task Priority register is not 
implemented with the processor, the Task Priority register should be 
updated only when the processor enter or exits an idle state.

Only when the Task Priority register is integrated within the processor, 
(such that it can be accessed as quickly as the MSRee bit defined in the 

 section, for example), should the architecture require 

the Task Priority register to be updated synchronously with instruction 
execution.