Motorola MVME172 用户手册
2-22
Computer Group Literature Center Web Site
VMEchip2
2
Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2)
DMA TB
SNP MODE
ROM
ZERO
SRAM
SPEED
ADDER
2
SLAVE ENDING ADDRESS 1
SLAVE ENDING ADDRESS 2
SLAVE ADDRESS TRANSLATION ADDRESS 1
SLAVE ADDRESS TRANSLATION ADDRESS 2
BLK
D64
D64
SNP
2
WP
2
SUP
2
USR
2
A32
2
A24
2
BLK
2
PRGM
2
DATA
2
2
MASTER ENDING ADDRESS 1
MASTER ENDING ADDRESS 2
MASTER ENDING ADDRESS 3
MASTER ENDING ADDRESS 4
MASTER ADDRESS TRANSLATION ADDRESS 4
VMEchip2 LCSR Base Address = $FFF40000
OFFSET:
OFFSET:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MAST
D16
EN
MAST
WP
EN
MAST
D16
EN
MAST
WP
EN
MASTER AM 3
MASTER AM 4
GCSR GROUP SELECT
GCSR
BOARD SELECT
MAST
4
EN
MAST
3
EN
MAST
2
EN
MAST
1
EN
TICK
2/1
TICK
IRQ 1
EN
CLR
IRQ
IRQ
STAT
VMEBUS
INTERRUPT
LEVEL
VMEBUS INTERRUPT VECTOR
0
4
8
C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
WAIT
RMW
RMW
DMA CONTROLLER
DMA CONTROLLER
DMA CONTROLLER
DMA CONTROLLER
This sheet continues on facing page.