用户手册目录Contents7FIGURES16TABLES16Board Description and Memory Maps19Introduction19Overview19Requirements22Block Diagrams23Functional Description23No-VMEbus-Interface Option23VMEbus Interface and VMEchip227Memory Maps27Local Bus Memory Map27Normal Address Range27Detailed I/O Memory Maps39BBRAM/TOD Clock Memory Map58Interrupt Acknowledge Map64VMEbus Memory Map64VMEbus Accesses to the Local Bus65VMEbus Short I/O Memory Map65Software Support Considerations65Interrupts65Cache Coherency66Sources of Local BERR*66Local Bus Time-out66VMEbus Access Time-out67VMEbus BERR*67Local DRAM Parity Error67VMEchip267Bus Error Processing67Description of Error Conditions on the MVME17268MPU Parity Error68MPU Off-board Error69MPU TEA Cause Unidentified69MPU Local Bus Time-out69DMAC VMEbus Error70DMAC Parity Error70DMAC Off-board Error71DMAC LTO Error71DMAC TEA Cause Unidentified72LAN Parity Error72LAN Off-Board Error73LAN LTO Error73SCSI Parity Error74SCSI Off-Board Error74SCSI LTO Error74Example of the Proper Use of Bus Timers75MVME172 MC68060 Indivisible Cycles76Illegal Access to IP Modules from External VMEbus Masters77VMEchip279Introduction79Summary of Major Features79Functional Blocks82Local Bus to VMEbus Interface82Local Bus to VMEbus Requester85VMEbus to Local Bus Interface87Local Bus to VMEbus DMA Controller88No Address Increment DMA Transfers90DMAC VMEbus Requester91Tick and Watchdog Timers92Prescaler92Tick Timers93Watchdog Timer93VMEbus Interrupter94VMEbus System Controller95Arbiter95IACK Daisy-Chain Driver95Bus Timer95Reset Driver96Local Bus Interrupter and Interrupt Handler96Global Control and Status Registers98LCSR Programming Model98Programming the VMEbus Slave Map Decoders104VMEbus Slave Ending Address Register 1106VMEbus Slave Starting Address Register 1106VMEbus Slave Ending Address Register 2107VMEbus Slave Starting Address Register 2107VMEbus Slave Address Translation Address Offset Register 1107VMEbus Slave Address Translation Select Register 1108VMEbus Slave Address Translation Address Offset Register 2109VMEbus Slave Address Translation Select Register 2109VMEbus Slave Write Post and Snoop Control Register 2110VMEbus Slave Address Modifier Select Register 2111VMEbus Slave Write Post and Snoop Control Register 1113VMEbus Slave Address Modifier Select Register 1114Programming the Local Bus to VMEbus Map Decoders115Local Bus Slave (VMEbus Master) Ending Address Register 1117Local Bus Slave (VMEbus Master) Starting Address Register 1118Local Bus Slave (VMEbus Master) Ending Address Register 2118Local Bus Slave (VMEbus Master) Starting Address Register 2118Local Bus Slave (VMEbus Master) Ending Address Register 3119Local Bus Slave (VMEbus Master) Starting Address Register 3119Local Bus Slave (VMEbus Master) Ending Address Register 4119Local Bus Slave (VMEbus Master) Starting Address Register 4120Local Bus Slave (VMEbus Master) Address Translation Address Register 4120Local Bus Slave (VMEbus Master) Address Translation Select Register 4120Local Bus Slave (VMEbus Master) Attribute Register 4121Local Bus Slave (VMEbus Master) Attribute Register 3122Local Bus Slave (VMEbus Master) Attribute Register 2123Local Bus Slave (VMEbus Master) Attribute Register 1124VMEbus Slave GCSR Group Address Register125VMEbus Slave GCSR Board Address Register126Local Bus to VMEbus Enable Control Register127Local Bus to VMEbus I/O Control Register128ROM Control Register129Programming the VMEchip2 DMA Controller130DMAC Registers131PROM Decoder, SRAM and DMA Control Register132Local Bus to VMEbus Requester Control Register133DMAC Control Register 1 (bits 07)134DMAC Control Register 2 (bits 815)135DMAC Control Register 2 (bits 07)137DMAC Local Bus Address Counter138DMAC VMEbus Address Counter138DMAC Byte Counter139Table Address Counter139VMEbus Interrupter Control Register139VMEbus Interrupter Vector Register141MPU Status and DMA Interrupt Count Register141DMAC Status Register142Programming the Tick and Watchdog Timers143VMEbus Arbiter Time-out Control Register143DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register144VME Access, Local Bus, and Watchdog Time-out Control Register145Prescaler Control Register146Tick Timer 1 Compare Register147Tick Timer 1 Counter147Tick Timer 2 Compare Register148Tick Timer 2 Counter148Board Control Register149Watchdog Timer Control Register150Tick Timer 2 Control Register151Tick Timer 1 Control Register152Prescaler Counter152Programming the Local Bus Interrupter153Local Bus Interrupter Status Register (bits 2431)156Local Bus Interrupter Status Register (bits 1623)157Local Bus Interrupter Status Register (bits 815)158Local Bus Interrupter Status Register (bits 07)159Local Bus Interrupter Enable Register (bits 2431)160Local Bus Interrupter Enable Register (bits 1623)161Local Bus Interrupter Enable Register (bits 815)162Local Bus Interrupter Enable Register (bits 07)163Software Interrupt Set Register (bits 815)164Interrupt Clear Register (bits 2431)164Interrupt Clear Register (bits 1623)165Interrupt Clear Register (bits 815)166Interrupt Level Register 1 (bits 2431)166Interrupt Level Register 1 (bits 1623)167Interrupt Level Register 1 (bits 815)167Interrupt Level Register 1 (bits 07)168Interrupt Level Register 2 (bits 2431)168Interrupt Level Register 2 (bits 1623)169Interrupt Level Register 2 (bits 815)169Interrupt Level Register 2 (bits 07)170Interrupt Level Register 3 (bits 2431)170Interrupt Level Register 3 (bits 1623)171Interrupt Level Register 3 (bits 815)171Interrupt Level Register 3 (bits 07)172Interrupt Level Register 4 (bits 2431)172Interrupt Level Register 4 (bits 1623)173Interrupt Level Register 4 (bits 815)173Interrupt Level Register 4 (bits 07)174Vector Base Register174I/O Control Register 1175I/O Control Register 2176I/O Control Register 3176Miscellaneous Control Register177GCSR Programming Model179Programming the GCSR181VMEchip2 Revision Register183VMEchip2 ID Register183VMEchip2 LM/SIG Register183VMEchip2 Board Status/Control Register185General Purpose Register 0186General Purpose Register 1186General Purpose Register 2187General Purpose Register 3187General Purpose Register 4188General Purpose Register 5188MC2 Chip189Introduction189Summary of Major Features189Functional Description190MC2 Chip Initialization190Flash and PROM Interface190BBRAM Interface19182596CA LAN Interface191MPU Port and MPU Channel Attention191MC68060-Bus Master Support for 82596CA192LANC Bus Error192LANC Interrupt19353C710 SCSI Controller Interface193SRAM Memory Controller193NON-ECC DRAM Memory Controller193Z85230 SCC Interface194Tick Timers195Watchdog Timer196Local Bus Timer196Memory Map of the MC2 Chip Registers196Programming Model198MC2 Chip ID Register199MC2 Chip Revision Register199General Control Register200Interrupt Vector Base Register201Programming the Tick Timers203Tick Timer 1 and 2 Compare and Counter Registers203LSB Prescaler Count Register205Prescaler Clock Adjust Register206Tick Timer 1 and 2 Control Registers206Tick Timer Interrupt Control Registers208DRAM Parity Error Interrupt Control Register210SCC Interrupt Control Register211Tick Timer 3 and 4 Control Registers212DRAM and SRAM Memory Controller Registers213DRAM Space Base Address Register213SRAM Space Base Address Register214DRAM Space Size Register214DRAM/SRAM Options Register215SRAM Space Size Register217LANC Error Status Register21882596CA LANC Interrupt Control Register219LANC Bus Error Interrupt Control Register220SCSI Error Status Register221General Purpose Inputs Register221MVME172 Version Register223SCSI Interrupt Control Register224Tick Timer 3 and 4 Compare and Counter Registers225Bus Clock Register226PROM Access Time Control Register227Flash Access Time Control Register228ABORT Switch Interrupt Control Register229RESET Switch Control Register230Watchdog Timer Control Register231Access and Watchdog Time Base Select Register232DRAM Control Register233MPU Status Register23432-bit Prescaler Count Register236IP2 Chip237Introduction237Summary of Major Features237Functional Description238General Description238Cache Coherency238Local Bus to IndustryPack DMA Controllers239Clocking Environments and Performance241Programmable Clock243Error Reporting243Error Reporting as a Local Bus Slave243Error Reporting as a Local Bus Master243IndustryPack Error Reporting244Interrupts244Overall Memory Map245Programming Model246Chip ID Register253Chip Revision Register253Vector Base Register254IP_a, IP_b, IP_c, IP_d Memory Base Address Registers255IP_a or Double Size IP_ab Memory Base Address Registers256IP_b Memory Base Address Registers256IP_c or Double Size IP_cd Memory Base Address Registers257IP_d Memory Base Address Registers257IP_a, IP_b, IP_c, IP_d Memory Size Registers257IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control Registers259IP_a, IP_b, IP_c, and IP_d; General Control Registers260IP Clock Register264DMA Arbitration Control Register265IP RESET Register266Programming the DMA Controllers267DMA Enable Function269DMA Control and Status Register Set Definition269Programming the Programmable Clock279Local Bus to IndustryPack Addressing2828-Bit Memory Space28216-Bit Memory Space28332-Bit Memory Space284IP_a I/O Space285IP_ab I/O Space286IP_a ID Space287IP to Local Bus Data Routing288Memory Space Accesses288I/O and ID Space Accesses290MCECC291Introduction291Features291Functional Description292General Description292Performance292Cache Coherency293ECC294Cycle Types294Error Reporting295Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)295Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)295Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)296Cycle Type = Burst Write296Single Bit Error (Cycle Type = Non-Burst Write)296Double Bit Error (Cycle Type = Non-Burst Write)296Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)296Single Bit Error (Cycle Type = Scrub)296Double Bit Error (Cycle Type = Scrub)297Triple (or Greater) Bit Error (Cycle Type = Scrub)297Error Logging297Scrub297Refresh298Arbitration298Chip Defaults298Programming Model299Chip ID Register304Chip Revision Register304Memory Configuration Register305Dummy Register 0306Dummy Register 1307Base Address Register307DRAM Control Register308BCLK Frequency Register310Data Control Register311Scrub Control Register313Scrub Period Register Bits 15-8314Scrub Period Register Bits 7-0314Chip Prescaler Counter315Scrub Time On/Time Off Register315Scrub Prescaler Counter (Bits 21-16)317Scrub Prescaler Counter (Bits 15-8)318Scrub Prescaler Counter (Bits 7-0)318Scrub Timer Counter (Bits 15-8)318Scrub Timer Counter (Bits 7-0)319Scrub Address Counter (Bits 26-24)319Scrub Address Counter (Bits 23-16)320Scrub Address Counter (Bits 15-8)320Scrub Address Counter (Bits 7-4)321Error Logger Register321Error Address (Bits 31-24)322Error Address (Bits 23-16)323Error Address Bits (15-8)323Error Address Bits (7-4)323Error Syndrome Register324Defaults Register 1324Defaults Register 2326Initialization327Syndrome Decode329Related Documentation333Motorola Computer Group Documents333Literature Updates334Manufacturers’ Documents334Using Interrupts on the MVME172337Introduction337VMEchip2 Tick Timer 1 Periodic Interrupt Example337Index341文件大小: 3.2 MB页数: 354Language: English打开用户手册