Motorola MVME172 用户手册
3-2
Computer Group Literature Center Web Site
MC2 Chip
3
Functional Description
The following sections provide an overview of the functions provided by
the MC2 chip. A detailed programming model for the MC2 chip control
and status registers is provided in a later section.
the MC2 chip. A detailed programming model for the MC2 chip control
and status registers is provided in a later section.
MC2 Chip Initialization
The MC2 chip ASIC is designed to accommodate several memory
configurations and MVME172 population versions. Configuration
registers are used to initialize the MVME172 Version Register, General
Purpose Inputs Register, and DRAM/SRAM Options Register (read only).
configurations and MVME172 population versions. Configuration
registers are used to initialize the MVME172 Version Register, General
Purpose Inputs Register, and DRAM/SRAM Options Register (read only).
Flash and PROM Interface
The MC2 chip interfaces the MC68060 local bus to one 2M X 8 Intel
28F016SA Flash device, and two 32-pin DIP JEDEC standard PROM
sockets for the 200/300-Series modules and one PLCC socket for 400/500-
Series modules. The Flash and PROM memory map locations can be
swapped based upon a jumper (J11, pins 7 and 8, GPI3) input to the
initialization PAL. (The initialization device was discussed in the previous
section.) This enables the MVME172 to execute reset code from either the
PROM or Flash.
28F016SA Flash device, and two 32-pin DIP JEDEC standard PROM
sockets for the 200/300-Series modules and one PLCC socket for 400/500-
Series modules. The Flash and PROM memory map locations can be
swapped based upon a jumper (J11, pins 7 and 8, GPI3) input to the
initialization PAL. (The initialization device was discussed in the previous
section.) This enables the MVME172 to execute reset code from either the
PROM or Flash.
The MC2 chip executes multiple cycles to the eight-bit Flash/PROM
devices so that byte, word, or longword accesses are allowed. Burst
accesses to Flash/PROM are inhibited by the interface so that they are
broken into four longword accesses.
devices so that byte, word, or longword accesses are allowed. Burst
accesses to Flash/PROM are inhibited by the interface so that they are
broken into four longword accesses.
The MC2 chip ASIC supports write cycles to EPROM memory space with
a normal cycle termination by asserting transfer acknowledge. Data is not
changed. The MC2 chip allows the write cycle to time out.
a normal cycle termination by asserting transfer acknowledge. Data is not
changed. The MC2 chip allows the write cycle to time out.
The Flash memory has a write-protect feature. A CSR bit in the Flash
Parameter Register (FWEN, bit 11) inhibits write cycles to Flash. Note that
there is also a jumper which will inhibit writes to Flash. Refer to your
MVME172 installation and use manual.
Parameter Register (FWEN, bit 11) inhibits write cycles to Flash. Note that
there is also a jumper which will inhibit writes to Flash. Refer to your
MVME172 installation and use manual.