Motorola MVME172 用户手册
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IP2 Chip
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indicates that a local bus error did occur as a consequence of a DMA
operation. The contents of the local bus address counter can be examined
for the address that caused the bus error.
operation. The contents of the local bus address counter can be examined
for the address that caused the bus error.
IndustryPack Error Reporting
Each IndustryPack interface has an error pin. The error status from the four
interfaces are available in the General Control Registers.
interfaces are available in the General Control Registers.
Interrupts
The IP2 chip can be programmed to interrupt the local bus master via the
IPL* signal pins when one or more of the eight IndustryPack interrupts are
asserted. The interrupt control registers allow each interrupt source to be
level/edge sensitive and high/low true.
IPL* signal pins when one or more of the eight IndustryPack interrupts are
asserted. The interrupt control registers allow each interrupt source to be
level/edge sensitive and high/low true.
When the local bus master acknowledges an interrupt, if the IP2 chip
determines that it is the source of the interrupt being acknowledged, it
waits for IACKIN* to be asserted, then it performs an interrupt
acknowledge cycle to the appropriate IndustryPack in order to obtain the
vector number. It then passes the vector number on to the local bus master
and asserts TA* to terminate the cycle.
determines that it is the source of the interrupt being acknowledged, it
waits for IACKIN* to be asserted, then it performs an interrupt
acknowledge cycle to the appropriate IndustryPack in order to obtain the
vector number. It then passes the vector number on to the local bus master
and asserts TA* to terminate the cycle.
When the local bus master acknowledges an interrupt, if the IP2 chip
determines that it is not the source of the interrupt being acknowledged, it
waits for IACKIN* to be asserted, then it passes the acknowledge on down
the daisy-chain by asserting IACKOUT*.
determines that it is not the source of the interrupt being acknowledged, it
waits for IACKIN* to be asserted, then it passes the acknowledge on down
the daisy-chain by asserting IACKOUT*.
The interrupter also provides interrupt capability for the programmable
clock and for each of the four DMA controllers. Additionally, interrupts
from the programmable clock can be programmed for rising and/or falling
edge sensitivity. The vector passed to the local bus master during an
interrupt acknowledge for the programmable clock and DMAC interrupts
is from the vector base register in the IP2 chip. Part of the vector is
programmable; the other part encodes the source of the interrupt.
clock and for each of the four DMA controllers. Additionally, interrupts
from the programmable clock can be programmed for rising and/or falling
edge sensitivity. The vector passed to the local bus master during an
interrupt acknowledge for the programmable clock and DMAC interrupts
is from the vector base register in the IP2 chip. Part of the vector is
programmable; the other part encodes the source of the interrupt.