Motorola MVME172 用户手册

Functional Description

http://www.mcg.mot.com/literature

5-3

Random, non-burst writes are the slowest kind of access because they 
require that the MCECC pair perform a read-modify-write cycle to the 
DRAM in order to complete. The MCECC pair responds to the local bus 
in two clocks during random writes, but then it takes another eight clocks 
for the DRAM read-modify-write cycle to complete, thereby making the 
effective cycle time 10 clocks if the following access by the local bus 
master is to DRAM. This boils down to two clocks for one random write, 
and 10 clocks for sustained random writes. 

The performance specifications for the MCECC are shown in 

. 

The MCECC pair supports the MC68060 caching scheme on the local bus 
by always providing 32 bits of valid data during DRAM read cycles 
regardless of the number of bytes requested by the local bus master for the 
cycle. It also supports cache coherency by monitoring the snoop control 
signal lines on the local bus and behaving appropriately based on their 
value. 

When the snoop control signal lines (SC1, SC0) indicate that snooping is 
inhibited, the MCECC pair ignores the memory inhibit (MI*) signal line. 

Reads, BERR off, FSTRD = 1

4 clock cycles for random reads

4-1-1-1 clock cycles for burst reads (sustained)

Reads, FSTRD = 0

5 clock cycles for random reads

5-1-1-1 clock cycles for burst reads (sustained)

Reads, BERR on

5 clock cycles for random reads

5-1-1-1 clock cycles for burst reads (sustained)

Writes

2 to 10 clock cycles for random non-burst writes

2-1-1-1 clock cycles for burst writes (sustained)