Motorola MVME172 用户手册

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页码 354
5-22
Computer Group Literature Center Web Site
MCECC
5
1. Stop all scrub operations by clearing all of the STON bits and setting 
all of the STOFF bits in the Scrub Time On/Time Off Register.
2. Set the DERC and RWCKB bits in the Data Control Register.
3. Perform the desired read and/or write checkbit operations.
4. Clear the DERC and RWCKB bits in the Data Control Register.
5. Perform the desired testing related to the location/locations that 
have had their checkbits altered.
6. Allow the scrubber to proceed by restoring the STON and STOFF 
bits to their original state.
ZFILL
ZERO FILL memory, when set, forces all zeros to be 
written to the DRAM during any kind of write cycle or 
scrub cycle. It is intended to be used with the zero-fill 
function. Refer to the section on Initialization at the end of 
this chapter. This bit should be cleared for normal system 
operation.
DERC
DISABLE ERROR CORRECTION, when set to one, 
disables the MCECC from correcting single bit errors. 
Specifically, read data is presented to the local MC68060 
data bus unaltered from the DRAM array. Less-than-line 
write data performs a read-modify-write without 
correcting single bit errors that may occur on the read 
portion of the read-modify-write. Note that DERC does 
not affect the generation of check bits. DERC should be 
cleared during normal system operation. DERC also 
allows the write portion of a read-modify-write to happen 
regardless of whether or not there is a multiple bit error 
during the read portion of the read-modify-write. DERC 
also affects scrub cycles.