Motorola MVME2600 用户手册
Memory Maps
http://www.motorola.com/computer/literature
2-5
2
Memory Maps
There are three points of view for memory maps:
❏
The mapping of all resources as viewed by the processor (MPU bus
memory map)
memory map)
❏
The mapping of onboard resources as viewed by PCI local bus
masters (PCI bus memory map)
masters (PCI bus memory map)
❏
The mapping of onboard resources as viewed by VMEbus masters
(VMEbus memory map)
(VMEbus memory map)
The following sections give a general description of the MVME2603/2604
memory organization from the above three points of view. Detailed
memory maps can be found in the MVME2600 Series Single Board
Computer Programmer’s Reference Guide, listed in
memory organization from the above three points of view. Detailed
memory maps can be found in the MVME2600 Series Single Board
Computer Programmer’s Reference Guide, listed in
.
Processor Memory Map
The processor memory map configuration is under the control of the
Raven bridge controller ASIC and the Falcon memory controller chip set.
The Raven and Falcon devices adjust system mapping to suit a given
application via programmable map decoder registers. At system power-up
or reset, a default processor memory map takes over.
Raven bridge controller ASIC and the Falcon memory controller chip set.
The Raven and Falcon devices adjust system mapping to suit a given
application via programmable map decoder registers. At system power-up
or reset, a default processor memory map takes over.