Motorola MVME2600 用户手册
2-6
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Operating Instructions
2
Default Processor Memory Map
The default processor memory map that is valid at power-up or reset
remains in effect until reprogrammed for specific applications.
remains in effect until reprogrammed for specific applications.
defines the entire default map ($00000000 to $FFFFFFFF).
further defines the map for the local I/O devices (accessible through the
PCI/ISA I/O Space).
PCI/ISA I/O Space).
Notes
1. Default map for PCI/ISA I/O space. Allows software to determine
whether the system is MPC105-based or Falcon/Raven-based by
examining either the PHB Device ID or the CPU Type register.
examining either the PHB Device ID or the CPU Type register.
2. The first 1MB of ROM/Flash bank A (soldered 4MB or 8MB
ROM/Flash) appears in this range after a reset if the rom_b_rv
control bit in the Falcon’s ROM B Base/Size register is cleared. If
the rom_b_rv control bit is set, this address range maps to
ROM/Flash bank B (socketed 1MB ROM/Flash).
control bit in the Falcon’s ROM B Base/Size register is cleared. If
the rom_b_rv control bit is set, this address range maps to
ROM/Flash bank B (socketed 1MB ROM/Flash).
Table 2-1. Processor Default View of the Memory Map
Processor Address
Size
Definition
Notes
Start
End
00000000
7FFFFFFF
2GB
Not Mapped
80000000
8001FFFF
128KB
PCI/ISA I/O Space
1
80020000
FEF7FFFF
2GB-16MB-
640KB
640KB
Not Mapped
FEF80000
FEF8FFFF
64KB
Falcon Registers
FEF90000
FEFEFFFF
384KB
Not Mapped
FEFF0000
FEFFFFFF
64KB
Raven Registers
FF000000
FFEFFFFF
15MB
Not Mapped
FFF00000
FFFFFFFF
1MB
ROM/Flash Bank A or
Bank B
Bank B
2