Intel MPCBL0010 用户手册

Intel NetStructure

®

 MPCBL0010 Single Board Computer

October 2006

Technical Product Specification

Order Number: 304120

139

The processor asserts IERR as the result of an internal error. A thermal trip error 

indicates the processor junction temperature has reached a level where permanent 

silicon damage may occur. Upon THERMTRIP assertion, the IPMC powers down the 

boards. This event is logged in the SEL.

The MCH instructs the ICH to report memory parity errors via SMI#. The SMI handler 

extracts the error information (address) from the DRAM error registers in the MCH and 

logs it into the SEL on the shelf manager. The KCS interface performs error reporting to 

the IPMC. The BIOS sends a platform event message with the appropriate data to the 

IPMC, which logs the event to the SEL on the shelf manager. Correctable memory 

errors generate an SMI and are logged into the SEL. Normally, a board with non-

correctable errors is likely to hang since the multi-bit error can cause the CPU to 

execute corrupted instructions. If the CPU executes corrupted instructions before 

executing the code to log the event, the event is not logged in the SEL.

The BIOS is able to log both POST and critical events to the IPMC error log.

In general, the system BIOS is capable of generating requests on the KCS interface to 

communicate with the IPMC for error logging, fault resilience, critical interrupts, and 

reading/writing inventory of CPU and RAM information to the IPMC. Two LPC interfaces 

are available for the BIOS to communicate with the IPMC. The BIOS uses the SMS 

interface for normal communication with the IPMC and the SMM interface when 

executing code under SMM mode.

PCI error handling is implemented in the MPCBL0010 SBC as follows:

1. The MCH sends a parity error/system error (PERR/SERR) message over the hub 

interface to the ICH notifying it that an error occurred.

2. The ICH generates an SMI# interrupt when it receives a PERR/SERR message.
3. The SMI handler checks the error status registers of the CPU/MCH until it identifies 

the source and type of the error.

4. The handler sends a message to the IPMC via the KCS interface, causing it to log 

the error in the IPMC and then forward the event to the shelf manager to log it into 

the SEL.

The MPCBL0010 SBC supports ACPI functionality with support for the sleep states S0, 

S4, and S5. The IPMC sends out a hot swap event message to the shelf manager 

requesting deactivation. On successful reception of a deactivation message from the 

shelf manager, the FRU enters M1 power state and remains in this state.

Under conditions where an ACPI enabled operating system is in S4/S5 sleep state, the 

chipset could de-assert, requiring the IPMC to attempt an AdvancedTCA power state 

transition to the M4 state (through M2, M3).

The ACPI capabilities of an operating system are communicated by the BIOS to the 

IPMC at initialization. An OEM-style IPMI command is sent by the BIOS for this 

purpose. This command is sent by the BIOS every time an operating system is