用户手册目录Contents3Figures8Tables9Revision History12Intel NetStructure® MPCBL0010 Single Board Computer11.0 Introduction131.1 Document Organization131.2 Glossary142.0 Feature Overview162.1 Application162.2 Functional Description16Figure 1. MPCBL0010 Block Diagram172.2.1 Low Voltage Intel® Xeon™ Processor172.2.2 Chipset172.2.2.1 Memory Controller Hub182.2.2.2 I/O Controller Hub182.2.2.3 64-Bit PCI Hub182.2.3 Memory (J10, J12)18Table 1. Supported Memory Configurations192.2.4 I/O192.2.4.1 I/O Controller Hub192.2.4.2 Real-Time Clock192.2.4.3 Timers192.2.4.4 Gigabit Ethernet202.2.4.5 10/100 Fast Ethernet202.2.4.6 USB 2.0202.2.4.7 Serial Ports202.2.5 AdvancedMC (AMC) Connector (J18, J19)202.2.6 Firmware Hubs212.2.6.1 FWH0 (Main BIOS)212.2.6.2 FWH1 (Backup/Recovery BIOS)222.2.6.3 Flash ROM Backup Mechanism222.2.7 Onboard Power Supplies222.2.7.1 Power Feed Fuses222.2.7.2 ORing Diodes and Circuit Breaker Protection222.2.7.3 Isolated -48 V to +12 V, 12 V Suspend, 5 V, 3.3 V Suspend, 1.8 V, and 1.5 V Converters222.2.7.4 Processor Voltage Regulator Module (VRM)232.2.7.5 IPMC Subsystem Standby Power232.2.7.6 Other On-board Supplies232.2.7.7 Other Suspend Power232.2.8 IPMC232.2.9 Telecom Clock232.2.10 AdvancedMC Direct Connect24Figure 2. AdvancedMCA Direct Connect Switch Block Diagram252.2.11 AdvancedTCA Compliance253.0 Operating the Unit263.1 Jumpers26Figure 3. Jumpers26Figure 4. Jumper/Connector Locations27Table 2. Jumper Definitions273.2 AdvancedMC Filler Panels28Figure 5. AdvancedMC Filler Panel283.3 Installing Memory29Figure 6. Memory Top Cover Installed29Figure 7. Empty DIMM Sockets29Figure 8. Memory Installed303.4 Installing and Extracting the SBC303.4.1 Chassis Installation313.4.2 Chassis Extraction313.5 AdvancedMC Module Installation and Extraction333.6 BIOS Configuration333.7 Remote Access Configuration333.8 Software Updates333.8.1 BIOS Updates343.8.2 Loading\Saving Custom BIOS Configuration343.8.2.1 Synchronizing BIOS Image and Settings from FWH0 (Main) to FWH1 (Backup)34Table 3. Suggested Method of BIOS Image Synchronization prior to BIOS Upgrade343.8.2.2 Copying BIOS.bin from the SBC353.8.2.3 Saving BIOS.bin to the SBC353.8.2.4 flashlnx Command Line Options36Table 4. Flashlnx Utility Command Line Options363.8.3 IPMC Firmware Updates363.8.3.1 IPMC Firmware Upgrade Using the KCS Interface363.9 Digital Ground to Chassis Ground Connectivity37Figure 9. Digital Ground and Chassis Ground Isolated (Default)374.0 Specifications384.1 Mechanical Specifications384.1.1 Board Outline384.1.2 Backing Plate and Top Cover384.2 Environmental Specifications38Table 5. Environmental Specifications (Sheet 1 of 2)384.3 Reliability Specifications394.3.1 Mean Time Between Failure (MTBF) Specifications39Table 6. Reliability Estimate Data394.3.1.1 Environmental Assumptions394.3.1.2 General Assumptions394.3.1.3 General Notes404.3.2 Power Requirements40Table 7. Power Requirements404.3.3 Power Consumption40Table 8. Total Measured Power404.4 Weight40Table 9. Weight405.0 Connectors and LEDs41Figure 10. Connector Locations42Table 10. On-board and Backplane Connector Assignments42Figure 11. Front Panel43Table 11. Front Panel Connector Assignments435.1 Backplane Connectors445.1.1 Power Distribution Connector (P10)44Figure 12. Power Distribution Connector (Zone 1) P1044Table 12. Power Distribution Connector (Zone 1) P10 Pin Assignments455.1.2 AdvancedTCA Data Transport Connector (J23)45Figure 13. Data Transport Connector (Zone 2) J2346Table 13. AdvancedTCA Data Transport Connector (Zone 2) J23 Pin Assignments475.1.3 AdvancedTCA Data Transport Connector (J20)47Table 14. AdvancedTCA* Data Transport Connector (Zone 2) J20 Pin475.1.4 Alignment Blocks475.2 On-Board Connectors485.2.1 POST Code Connector (J13)48Table 15. POST Code Connector Pin Assignments485.2.2 Extended IPT700 Debug Port Connector (J25)485.3 Front Panel Connectors495.3.1 Ethernet 10/100 Debug Connector (J3)49Figure 14. Ethernet 10/100 Debug Connector49Table 16. Ethernet 10/100 Debug Connector Pin Assignments49Table 17. Ethernet 10/100 Debug Connector LED Operation495.3.2 USB Connector (J4)50Figure 15. USB Connector (J4)50Table 18. USB Connector (J4) Pin Assignments505.3.3 Serial Port Connector (J5)50Figure 16. Serial Port Connector (J5)50Table 19. Serial Port Connector (J5) Pin Assignments51Figure 17. DB-9 to RJ-45 Pin Translation515.3.4 AdvancedMC* Connectors (J18, J19)51Table 20. AdvancedMC* Connector Pin Assignments52Figure 18. AdvancedMC* Connector535.4 LEDs53Figure 19. Front Panel LEDs (Option 1)54Figure 20. Front Panel B LEDs (Option 2)54Table 21. Front Panel LED Descriptions (Sheet 1 of 2)55Table 22. Ethernet 10/100 Debug Connector LED Operation565.4.1 POST LED Codes56Figure 21. Example POST LED Codes575.5 Reset Button576.0 BIOS Features586.1 Introduction586.2 BIOS Flash Memory Organization586.3 Complementary Metal-Oxide Semiconductor (CMOS)586.4 Redundant BIOS Functionality586.5 Legacy USB Support596.5.1 Language Support596.6 Recovering BIOS Data596.7 Boot Options596.7.1 CD-ROM and Network Boot606.7.2 Booting without Attached Devices606.8 Fast Booting Systems606.8.1 Quick Boot606.9 BIOS Security Features60Table 23. Supervisor and User Password Functions616.10 Remote Access Configuration61Table 24. Function Key Escape Code Equivalents (Sheet 1 of 2)617.0 BIOS Setup637.1 Introduction63Table 25. BIOS Setup Program Menu Bar63Table 26. BIOS Setup Program Function Keys637.2 Main Menu63Table 27. Main Menu647.3 Advanced Menu64Table 28. Advanced Menu657.3.1 CPU Configuration Sub-Menu65Table 29. CPU Configuration Sub-Menu667.3.2 IDE Configuration Sub-Menu66Table 30. IDE Configuration Sub-Menu677.3.2.1 Primary IDE Master/Slave Configuration Options68Table 31. IDE Master/Slave Sub-Menu687.3.3 SuperIO Configuration Sub-Menu69Table 32. SuperIO Configuration Sub-Menu707.3.4 ACPI Configuration Sub-Menu70Table 33. ACPI Configuration Sub-Menu717.3.4.1 Advanced ACPI Configuration Sub-Menu71Table 34. Advanced ACPI Configuration Sub-Menu717.3.4.2 Chipset ACPI Configuration Sub-Menu71Table 35. Chipset ACPI Configuration Sub-Menu727.3.5 System Management Sub-Menu72Table 36. System Management Sub-Menu737.3.6 Event Log Configuration Sub-Menu73Table 37. Event Log Configuration Sub-Menu747.3.6.1 PCI Express Error Masking Configuration Sub-Menu74Table 38. PCI Express Error Masking Configuration Sub-Menu747.3.7 MPS Configuration Sub-Menu75Table 39. MPS Configuration Sub-Menu757.3.8 AdvancedTCA* Channel Routing (PICMG*) Sub-Menu75Table 40. AdvancedTCA Channel Routing (PICMG) Sub-Menu767.3.9 On-board Devices Configuration Sub-Menu76Table 41. On-board Devices Configuration Sub-Menu77Table 42. Option ROM Configuration Options777.3.10 PCI Express* Configuration Sub-Menu77Table 43. PCI Express* Configuration Sub-Menu787.3.11 Remote Access Configuration Sub-Menu78Table 44. Remote Access Configuration Sub-Menu797.3.12 IPMI Configuration Sub-Menu79Table 45. IPMI Configuration Sub-Menu80Table 46. LAN Configuration Sub-Menu807.3.13 USB Configuration Sub-Menu81Table 47. USB Configuration Sub-Menu817.3.13.1 USB Mass Storage Device Configuration82Table 48. USB Mass Storage Device Configuration827.4 PCIPnP Menu82Table 49. PCIPnP Menu827.5 Boot Menu83Table 50. Boot Menu837.5.1 Boot Settings Configuration Sub-Menu83Table 51. Boot Settings Configuration Sub-Menu (Sheet 1 of 2)837.5.2 Boot Device Priority Sub-Menu84Table 52. Boot Device Priority Sub-Menu847.5.3 Hard Disk Drives Sub-menu85Table 53. Hard Disk Drive Sub-Menu857.5.4 OS Load Timeout Timer Sub-Menu85Table 54. OS Load Timeout Timer Sub-Menu867.6 Security Menu86Table 55. Security Menu867.7 Chipset Menu86Table 56. Chipset Menu877.7.1 Northbridge Configuration Sub-Menu87Table 57. Northbridge Chipset Configuration877.7.2 Spread Spectrum Clocking Mode Sub-Menu88Table 58. Spread Spectrum Clocking Mode Configuration887.8 Exit Menu88Table 59. Exit Menu888.0 Error Messages908.1 BIOS Error Messages90Table 60. BIOS Error Messages908.2 Port 80h POST Codes90Table 61. Bootblock Initialization Code Checkpoints91Table 62. POST Code Checkpoints91Table 63. DIM Code Checkpoints93Table 64. ACPI Runtime Checkpoints939.0 Addressing949.1 PCI Configuration Map94Table 65. PCI Configuration Map949.2 FPGA Registers96Table 66. FPGA Register Legend96Table 67. FPGA Register Overview97Table 68. POST Codes 00:80h97Table 69. Extended POST Codes 0081h97Table 70. FPGA Version 0A00h98Table 71. Debug LED 0A01h98Table 72. FWUM 0A02h99Table 73. Development Features 0A04h99Table 74. Telecom Clock Register 0 0A08h100Table 75. Telecom Clock Register 1 0A09h101Table 76. Telecom Clock Register 2 0A0Ah101Table 77. Telecom Clock Register 3 0A0Bh102Table 78. Transmission Frequency Selection102Table 79. Telecom Clock Register 4 0A0Ch102Table 80. Telecom Clock Register 5 0A0Dh103Table 81. Telecom Clock Register 6 0A0Eh103Table 82. Telecom Clock Register 7 0A0Fh1049.3 IPMC Addresses104Table 83. IPMC Register Legend104Table 84. SBC Control 00h1059.3.0.1 PwrBtn usage106Table 85. SBC Status 01h107Table 86. POST Code Low 02h107Table 87. POST Code High 03h107Table 88. LED Color Control 06h107Table 89. LED Control 07h107Table 90. AdvancedMC B1 Control & Status 10h108Table 91. AdvancedMC B1 Control & Status 11h108Table 92. AMC B2 Control & Status 12h109Table 93. AdvancedMC B2 Control & Status 13h109Table 94. CPU 0 VIDs 18h110Table 95. CPU 0 Status 19h110Table 96. ADC Grab Control 20h110Table 97. ADC1 and ADC2 Grab Data 21-22h111Table 98. Fabric Control 1 24h111Table 99. Fabric Control 2 25h112Table 100. Reset Source 27h112Table 101. Firmware Hub Control 28h112Table 102. Reset Events 29h112Table 103. Crosspoint Switch Control 2Ah113Table 104. Crosspoint Switch Ports Register114Table 105. Crosspoint Switch Data 2Bh114Table 106. Miscellaneous Controls and Status 2Dh114Table 107. IPMC POST Codes FEh114Table 108. Version FFh11510.0 Hardware Management Overview11610.1 Intelligent Platform Management Controller (IPMC)116Figure 22. IPMC Block Diagram11710.2 Sensor Data Record (SDR)118Table 109. Hardware Sensors (Sheet 1 of 4)118Table 110. OEM Sensor Types121Table 111. OEM Event/Reading Type12210.3 System Event Log (SEL)122Table 112. SEL Events Supported (Sheet 1 of 5)12210.4 IPMB Link Sensor12710.5 Field Replaceable Unit (FRU) Information127Table 113. FRU Multi-Record Data for CPU/RAM/PMC/BIOS Version Information12710.6 Customizable FRU Area12810.6.1 LinuxCustFru Utility Usage12810.6.2 FRU Customer Area12810.7 E-Keying13110.8 OEM IPMI Commands13110.8.1 Reset BIOS Flash Type132Table 114. Reset BIOS Flash Type13210.8.2 Board Device Channel Port Selection Identifiers132Table 115. Channel Port Selection Identifiers132Figure 23. AdvancedMC Direct Connect Switch Block Diagram13310.8.2.1 SetBoardDeviceChannelPortSelection133Table 116. SetBoardDeviceChannelPortSelection13310.8.2.2 GetBoardDeviceChannelPortSelection134Table 117. GetBoardDeviceChannelPortSelection13410.8.2.3 GetBoardDevicePossibleSelection134Table 118. GetBoardDevicePossibleSelection13410.8.3 Set Control State135Table 119. Set Control State13510.8.4 Get Control State135Table 120. Get Control State13510.8.5 Controls Identifier Table135Table 121. Controls Identifier13610.9 Hot Swap Process136Figure 24. Hot Swap Process13610.9.1 Hot Swap LED137Table 122. Hot Swap LED Signals13710.10 AdvancedMC Module Activation13710.10.1 Pre-Defined Resources for AdvancedMC Modules13810.11 Temperature and Voltage Sensors138Table 123. Sensors and Thresholds (Version SDR 040)13910.11.1 Processor Events14010.11.2 DIMM Memory Events14010.11.3 System Firmware Progress (POST Error)14010.11.4 Critical Interrupts14010.11.5 System ACPI Power State14010.11.6 IPMB Link Sensor14110.11.7 FRU Hot Swap14110.12 Reset141Table 124. Reset Actions14110.12.1 Warm Reset142Figure 25. Warm Reset Block Diagram14210.12.2 Hard Reset14210.13 Field Replaceable Unit (FRU) Information14210.14 IPMC Firmware Code143Figure 26. IPMC Firmware Code Process14411.0 Serial Over LAN (SOL)14611.1 References14611.2 SOL Architecture14611.2.1 SOL Implementation146Figure 27. SOL Block Diagram14711.2.2 Architectural Components14811.2.2.1 IPMC14811.2.2.2 Ethernet Controller14811.3 Theory of Operation14811.3.1 Front Panel Serial Port or Rear Transition Module14811.3.2 Serial Over LAN14811.4 Serial Over LAN Client14911.5 Reference Configuration Script14911.6 Supported Usage Model150Figure 28. Reference Script Running on a Remote Node, Communicating over the LAN15011.6.1 Configuring the Blade for SOL15011.7 Reference Script (reference_cfg)15111.7.1 SOL Configuration Reference Script (reference_cfg)15111.7.2 Default Behavior15111.7.3 SOL User Information15111.7.4 LAN Parameters15111.7.5 SOL Parameters15211.7.6 Channel Parameters15211.7.7 Command Line Options152Table 125. SOL Configuration Reference Script Command-line Options15211.8 Setting up a Serial Over LAN Session15311.8.1 Target Blade Setup15311.8.1.1 BIOS Configuration153Figure 29. BIOS Configuration of SOL Target Blade15411.8.1.2 Operating System Configuration154Figure 30. Configuration for RHEL15511.8.1.3 sbcutils RPM Installation15611.8.1.4 Execute the reference_cfg Script15611.8.2 Client Blade Setup15811.8.2.1 Configure the Ethernet Port15811.8.2.2 Installing ipmitool15911.8.2.3 Start an SOL Session15911.8.2.4 Checking SOL Configuration15911.8.2.5 Ending an SOL Session16011.9 Operating Systems for SOL Client (ipmitool)16112.0 Telecom Clock16212.1 Functional Description162Figure 31. Block Diagram of the Telecom Clock16212.2 Interface Description16312.2.1 AdvancedTCA Backplane Interface16312.2.2 AdvancedMC Interface16312.2.3 Reset/Interrupt Interface16312.2.4 LPC Interface16312.3 Function Description16312.3.1 Redundant Reference Clock Selection16312.3.2 PLL Clock Generation16312.3.3 Recovered Clock Selection16412.3.4 Configuration16412.3.4.1 Operational Configuration16412.3.5 Alarm Handling16412.4 Telecom Clock API16512.4.1 TRANSMIT CLOCK165Table 126. Module Transmission Frequency Selection16512.4.2 Enable/Disable Transmission Clock16512.4.3 Recovered Clock16612.4.4 Automatic Switchover166Table 127. Automatic Switchover Values16612.4.5 Automatic Switchover Mode166Table 128. Switchover Mode Values16712.4.6 Select Reference Clock167Table 129. Received Reference Clock Values16712.4.7 Reference Frequency for PLL167Table 130. Reference Frequency PLL Values16712.4.8 Primary/Secondary Redundant Clock167Table 131. Primary/Secondary Redundant Clock Values16712.4.9 Corner Frequency168Table 132. Corner Frequency Values16812.4.10 PLL Operating Mode168Table 133. PLL Operating Mode Values16812.4.11 Reference Clock Alignment16812.4.12 Hardware Reset168Table 134. Hardware Reset Values16912.4.13 Read Alarm States169Table 135. Alarm State Values16912.4.14 Read New Events169Table 136. New Event Values16912.4.15 Read the Current Reference Clock170Table 137. Reference Clock Values17012.4.16 sysfs Interface170Table 138. Telecom Clock API Function Mapping for the sysfs Interface17012.5 Telecom Clock Registers171Table 139. FPGA Register Legend171Table 140. FPGA Register Overview171Table 141. Telecom Clock Register 0 0A08h172Table 142. Telecom Clock Register 1 0A09h172Table 143. Telecom Clock Register 2 0A0Ah173Table 144. Telecom Clock Register 3 0A0Bh174Table 145. Transmission Frequency Selection174Table 146. Telecom Clock Register 4 0A0Ch174Table 147. Telecom Clock Register 5 0A0Dh175Table 148. Telecom Clock Register 6 0A0Eh175Table 149. Telecom Clock Register 7 0A0Fh175Table 150. FPGA/PLD Serial Link Bit Definition17713.0 Maintenance17813.1 Supervision178Table 151. Hardware Monitoring Components17813.2 Diagnostics17813.2.1 In-Target Probe (ITP)17814.0 Thermals179Figure 32. Power vs. Flow Rate17915.0 Component Technology18016.0 Warranty Information18116.1 Intel NetStructure® Compute Boards and Platform Products Limited Warranty18116.2 Returning a Defective Product (RMA)18116.3 For the Americas18116.3.1 For Europe, Middle East, and Africa (EMEA)18216.3.2 For Asia and Pacific (APAC)18216.3.3 Limitation of Liability and Remedies18217.0 Customer Support18417.1 Customer Support18417.2 Technical Support and Return for Service Assistance18417.3 Sales Assistance18417.4 Product Code Summary184Table 152. Product Codes18418.0 Certifications18519.0 Agency Information-Class B18619.1 North America (FCC Class B)18619.2 Canada - Industry Canada (ICES-003 Class B) (English and French-translated)18619.3 Japan VCCI Class B18619.4 Korean Class B18719.5 Australia, New Zealand18720.0 Safety Warnings18820.1 Mesures de Sécurité18920.2 Sicherheitshinweise19020.3 Norme di Sicurezza19120.4 Instrucciones de Seguridad19220.5 Chinese Safety Warning193Appendix A Reference Documents194Appendix B List of Supported Commands (IPMI v1.5 and PICMG 3.0)196Table 153. IPMI 1.5 Supported Commands (Sheet 1 of 2)196Table 154. PICMG 3.0 IPMI Supported Commands198文件大小: 3.0 MB页数: 198Language: English打开用户手册