Intel IXP42X 用户手册

Intel

®

 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

September 2006

DM

Order Number: 252480-006US

339

Leaving loop-back mode and returning to normal mode may result in unpredictable 

activation of the Modem Status Register (MSR). It is recommended that the Modem 

Status Register be read once to clear the Modem Status Bits in the Modem Status 

Register. 

In the loop-back diagnostic mode, data that is transmitted will be immediately 

received. The ability to loop back the transmit data path to the receive path allows the 

Intel XScale processor to verify the transmit data path and receive data path of the 

UART. The transmit interrupts, receive interrupts, and modem-control interrupts are 

operational, when placed in the loop-back diagnostic mode. The Modem-Control 

Register Bits — instead of the Modem Control inputs — will activate the modem-control 

interrupts. A break signal can also be transferred — from the transmitter section to the 

receiver section — while operating in loop-back diagnostic mode.

Bit 1 of the Modem-Control Register is the Request-to-Send Bit. The Request-to-Send 

Control Bit is used to program the RTS_N output pin. When the Request-to-Send 

control bit is programmed to logic 0, the RTS_N signal will output logic 1. When the 

Request-to-Send Control Bit is programmed to logic 1, the RTS_N signal will output 

logic 0.

The Modem-Status Register is used to monitor the status of an external modem or data 

set. The Modem Status Register is an 8-bit register that is used to detect when a 

modem is capable of accepting new data. The status of the modem to accept incoming 

data is monitored by reading the Clear-to-Send Bit of the Modem Status Register and 

the Delta Clear-to-Send Bit of the Modem Status Register. The other six bits of the 

Modem-Status Register can be used for UART debug purposed only.

Modem Status Register Bit 4 is the Clear-to-Send (CTS). The Clear-to-Send Bit will be 

the complement of the Clear-to-Send (CTS_N) input signal. The Clear-to-Send signal 

will be connected to the Ready-to-Send bit of the Modem Control Register when the 

LOOP bit — in the Modem Control Register — is set to logic 1.

• CTS = logic 0 = CTS_N pin is 1
• CTS = logic 1 = CTS_N pin is 0

Modem Status Register Bit 0 is the Delta Clear-to-Send (DCTS). The Delta Clear-to-

Send bit will inform the IXP42X product line and IXC1100 control plane processors that 

nothing has happened to the Clear-to-Send Status since the last time that the Modem-

Status Register was read. The Delta Clear-to-Send bit will be set to logic 0 after a read 

of the Modem-Status Register.

• DCTS = logic 0 = No change in CTS_N pin since last read of the Modem-Status 

Register

• DCTS = logic 1 = CTS_N pin has changed state since the last read of the Modem-

Status Register

The Modem-Control Register is initialized to hexadecimal 0x00 after reset. The Modem-

Status Register is initialized to hexadecimal 0x00 after reset.

The UART Interrupt Enable Register (IER) is an 8-bit register that enables five types of 

UART based interrupts and enables the UART functionality and other control 

functionality not used by the IXP42X product line and IXC1100 control plane 

processors. 

UART Interrupt Enable Register bit 6 is the UART Unit Enable (UUE) bit. When the UART 

Unit Enable bit is set to logic 0, the UART will be completely non-functional. Likewise, 

when the UART Unit Enable bit is set to logic 1, the UART will be enabled.