Intel IXP42X 用户手册

Intel

®

 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

DM

September 2006

340

Order Number: 252480-006US

UART Interrupt Enable Register bits 4 through 0 represent five different interrupt types 

that can be individually enabled/disabled:

• Receiver Time Out Interrupt Enable (RTOIE)
• Modem Interrupt Enable (MIE)
• Receiver Line Status Interrupt Enable (RLSE)
• Transmit Data Request Interrupt Enable (TIE)
• Receiver Data Available Interrupt Enable (RAVIE)

The Receiver Line Status Interrupt Enable allows interrupts to be generated to the 

IXP42X product line and IXC1100 control plane processors Interrupt Controller and 

captured in the UART Interrupt Identification Register (IIR) when a receive error is 

detected. Such Receiver Line Status Conditions that would cause the interrupt to occur 

are:

In FIFO mode, each received character carries the line status along with the character. 

When in FIFO Mode, the Receive Line Status Interrupt will be active on the character 

located in the bottom of the Receive FIFO. If a Line Status error condition is detected 

on the character in the bottom of the Receive FIFO, a Receive Line Status Interrupt is 

generated. Reading the Line Status Register clears the Receive Line Status Interrupt. 

When in Non-FIFO Mode, the Receive Line Status Interrupt will be active on the 

character located in the bottom of the Receive Buffer Register. If a line-status error 

condition is detected on the character in the Receive Buffer Register, a Receive Line 

Status Interrupt is generated. 

The Receiver Data Available Interrupt Enable allows interrupts to be generated to the 

IXP42X product line and IXC1100 control plane processors’ Interrupt Controller and 

captured in the UART Interrupt Identification Register (IIR) when UART data is available 

to be read by the Intel XScale processor. 

When the UART is in FIFO mode, the Receive Data Available interrupt will be encoded in 

the Interrupt Identification Register, after the FIFO trigger level defined in the FIFO 

Control Register (FCR) is reached. When the UART is in non-FIFO mode, the Receive 

Data Available interrupt will be encoded in the Interrupt Identification Register after 

data is in the Receive Buffer Register (RBR). 

When operating in FIFO Mode, the Receive Data Available Interrupt is cleared, when 

the FIFO drops below the programmed trigger level. When operating in Non-FIFO 

Mode, the Receive Data Available Interrupt is cleared when the received character is 

read by the IXP42X product line and IXC1100 control plane processors from the 

Receive Holding Register.

The Receiver Interrupt Time Out Enable can be used only in FIFO Mode and allows 

interrupts to be generated to the IXP42X product line and IXC1100 control plane 

processors’ Interrupt Controller and captured in the UART Interrupt Identification 

Register (IIR). This happens when: 

• At least one character is available in the receive FIFO
• The last character received by the UART receive interface occurred more than four 

continuous character times ago

• The most-recent read of the receive FIFO, by the IXP42X product line and IXC1100 

control plane processors, was more than four continuous character times ago

• Overrun

• Parity

• Framing

• Break

• FIFO error