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5.25 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
5.26 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)
Ethernet Media Access Controller (EMAC) Registers
The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in
and described in
.
Figure 51. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXFILTERTHRESH
R-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 50. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXFILTERTHRESH
0-FFh
Receive filter low threshold. These bits contain the free buffer count threshold value for filtering
low priority incoming frames. This field should remain 0, if no filtering is desired.
low priority incoming frames. This field should remain 0, if no filtering is desired.
The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in
and
described in
Figure 52. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXnFLOWTHRESH
R-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 51. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXnFLOWTHRESH
0-FFh
Receive flow threshold. These bits contain the threshold value for issuing flow control on
incoming frames for channel n (when enabled).
incoming frames for channel n (when enabled).
92
Ethernet Media Access Controller (EMAC)/
SPRU941A – April 2007
Management Data Input/Output (MDIO)