用户手册目录Table of Contents3Preface101 Introduction111.1 Purpose of the Peripheral111.2 Features111.3 Functional Block Diagram121.4 Industry Standard(s) Compliance Statement132 Peripheral Architecture132.1 Clock Control132.2 Memory Map132.3 Signal Descriptions132.4 Ethernet Protocol Overview152.4.1 Ethernet Frame Format152.4.2 Ethernet’s Multiple Access Protocol162.5 Programming Interface162.5.1 Packet Buffer Descriptors162.5.2 Transmit and Receive Descriptor Queues182.5.3 Transmit and Receive EMAC Interrupts192.5.4 Transmit Buffer Descriptor Format202.5.4.1 Next Descriptor Pointer212.5.4.2 Buffer Pointer212.5.4.3 Buffer Offset212.5.4.4 Buffer Length212.5.4.5 Packet Length212.5.4.6 Start of Packet (SOP) Flag212.5.4.7 End of Packet (EOP) Flag222.5.4.8 Ownership (OWNER) Flag222.5.4.9 End of Queue (EOQ) Flag222.5.4.10 Teardown Complete (TDOWNCMPLT) Flag222.5.4.11 Pass CRC (PASSCRC) Flag222.5.5 Receive Buffer Descriptor Format232.5.5.1 Next Descriptor Pointer232.5.5.2 Buffer Pointer232.5.5.3 Buffer Offset242.5.5.4 Buffer Length252.5.5.5 Packet Length252.5.5.6 Start of Packet (SOP) Flag252.5.5.7 End of Packet (EOP) Flag252.5.5.8 Ownership (OWNER) Flag252.5.5.9 End of Queue (EOQ) Flag252.5.5.10 Teardown Complete (TDOWNCMPLT) Flag262.5.5.11 Pass CRC (PASSCRC) Flag262.5.5.12 Jabber Flag262.5.5.13 Oversize Flag262.5.5.14 Fragment Flag262.5.5.15 Undersized Flag262.5.5.16 Control Flag262.5.5.17 Overrun Flag262.5.5.18 Code Error (CODEERROR) Flag262.5.5.19 Alignment Error (ALIGNERROR) Flag262.5.5.20 CRC Error (CRCERROR) Flag262.5.5.21 No Match (NOMATCH) Flag272.6 EMAC Control Module272.6.1 Internal Memory272.6.2 Bus Arbiter272.6.3 Interrupt Control282.7 MDIO Module282.7.1 MDIO Module Components282.7.1.1 MDIO Clock Generator292.7.1.2 Global PHY Detection and Link State Monitoring292.7.1.3 Active PHY Monitoring292.7.1.4 PHY Register User Access292.7.2 MDIO Module Operational Overview302.7.2.1 Initializing the MDIO Module312.7.2.2 Writing Data To a PHY Register312.7.2.3 Reading Data From a PHY Register312.7.2.4 Example of MDIO Register Access Code322.8 EMAC Module332.8.1 EMAC Module Components332.8.1.1 Receive DMA Engine332.8.1.2 Receive FIFO332.8.1.3 MAC Receiver332.8.1.4 Transmit DMA Engine342.8.1.5 Transmit FIFO342.8.1.6 MAC Transmitter342.8.1.7 Statistics Logic342.8.1.8 State RAM342.8.1.9 EMAC Interrupt Controller342.8.1.10 Control Registers and Logic342.8.1.11 Clock and Reset Logic342.8.2 EMAC Module Operational Overview342.9 Media Independent Interface (MII)352.9.1 Data Reception352.9.1.1 Receive Control352.9.1.2 Receive Inter-Frame Interval352.9.1.3 Receive Flow Control352.9.2 Data Transmission372.9.2.1 Transmit Control372.9.2.2 CRC Insertion372.9.2.3 Adaptive Performance Optimization (APO)372.9.2.4 Interpacket-Gap (IPG) Enforcement372.9.2.5 Back Off372.9.2.6 Transmit Flow Control382.9.2.7 Speed, Duplex, and Pause Frame Support382.10 Packet Receive Operation392.10.1 Receive DMA Host Configuration392.10.2 Receive Channel Enabling392.10.3 Receive Address Matching392.10.4 Hardware Receive QOS Support402.10.5 Host Free Buffer Tracking402.10.6 Receive Channel Teardown402.10.7 Receive Frame Classification412.10.8 Promiscuous Receive Mode412.10.9 Receive Overrun432.11 Packet Transmit Operation442.11.1 Transmit DMA Host Configuration442.11.2 Transmit Channel Teardown442.12 Receive and Transmit Latency442.13 Transfer Node Priority452.14 Reset Considerations452.14.1 Software Reset Considerations452.14.2 Hardware Reset Considerations462.15 Initialization462.15.1 Enabling the EMAC/MDIO Peripheral462.15.2 EMAC Control Module Initialization462.15.3 MDIO Module Initialization472.15.4 EMAC Module Initialization482.16 Interrupt Support492.16.1 EMAC Module Interrupt Events and Requests492.16.1.1 Transmit Packet Completion Interrupts492.16.1.2 Receive Packet Completion Interrupts492.16.1.3 Statistics Interrupt502.16.1.4 Host Error Interrupt502.16.2 MDIO Module Interrupt Events and Requests512.16.2.1 Link Change Interrupt512.16.2.2 User Access Completion Interrupt512.16.3 Proper Interrupt Processing512.16.4 Interrupt Multiplexing512.17 Power Management522.18 Emulation Considerations523 EMAC Control Module Registers533.1 EMAC Control Module Interrupt Control Register (EWCTL)533.2 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)544 MDIO Registers554.1 MDIO Version Register (VERSION)554.2 MDIO Control Register (CONTROL)564.3 PHY Acknowledge Status Register (ALIVE)574.4 PHY Link Status Register (LINK)574.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)584.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)594.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)604.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)614.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)624.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)634.11 MDIO User Access Register 0 (USERACCESS0)644.12 MDIO User PHY Select Register 0 (USERPHYSEL0)654.13 MDIO User Access Register 1 (USERACCESS1)664.14 MDIO User PHY Select Register 1 (USERPHYSEL1)675 Ethernet Media Access Controller (EMAC) Registers685.1 Transmit Identification and Version Register (TXIDVER)715.2 Transmit Control Register (TXCONTROL)715.3 Transmit Teardown Register (TXTEARDOWN)725.4 Receive Identification and Version Register (RXIDVER)735.5 Receive Control Register (RXCONTROL)735.6 Receive Teardown Register (RXTEARDOWN)745.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)755.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)765.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)775.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)785.11 MAC Input Vector Register (MACINVECTOR)795.12 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)805.13 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)815.14 Receive Interrupt Mask Set Register (RXINTMASKSET)825.15 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)835.16 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)845.17 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)845.18 MAC Interrupt Mask Set Register (MACINTMASKSET)855.19 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)855.20 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)865.21 Receive Unicast Enable Set Register (RXUNICASTSET)895.22 Receive Unicast Clear Register (RXUNICASTCLEAR)905.23 Receive Maximum Length Register (RXMAXLEN)915.24 Receive Buffer Offset Register (RXBUFFEROFFSET)915.25 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)925.26 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)925.27 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)935.28 MAC Control Register (MACCONTROL)945.29 MAC Status Register (MACSTATUS)965.30 Emulation Control Register (EMCONTROL)985.31 FIFO Control Register (FIFOCONTROL)985.32 MAC Configuration Register (MACCONFIG)995.33 Soft Reset Register (SOFTRESET)995.34 MAC Source Address Low Bytes Register (MACSRCADDRLO)1005.35 MAC Source Address High Bytes Register (MACSRCADDRHI)1005.36 MAC Hash Address Register 1 (MACHASH1)1015.37 MAC Hash Address Register 2 (MACHASH2)1015.38 Back Off Test Register (BOFFTEST)1025.39 Transmit Pacing Algorithm Test Register (TPACETEST)1025.40 Receive Pause Timer Register (RXPAUSE)1035.41 Transmit Pause Timer Register (TXPAUSE)1035.42 MAC Address Low Bytes Register (MACADDRLO)1045.43 MAC Address High Bytes Register (MACADDRHI)1045.44 MAC Index Register (MACINDEX)1055.45 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)1065.46 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)1065.47 Transmit Channel 0-7 Completion Pointer Register (TXnCP)1075.48 Receive Channel 0-7 Completion Pointer Register (RXnCP)1075.49 Network Statistics Registers1085.49.1 Good Receive Frames Register (RXGOODFRAMES)1085.49.2 Broadcast Receive Frames Register (RXBCASTFRAMES)1085.49.3 Multicast Receive Frames Register (RXMCASTFRAMES)1085.49.4 Pause Receive Frames Register (RXPAUSEFRAMES)1095.49.5 Receive CRC Errors Register (RXCRCERRORS)1095.49.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)1095.49.7 Receive Oversized Frames Register (RXOVERSIZED)1095.49.8 Receive Jabber Frames Register (RXJABBER)1105.49.9 Receive Undersized Frames Register (RXUNDERSIZED)1105.49.10 Receive Frame Fragments Register (RXFRAGMENTS)1105.49.11 Filtered Receive Frames Register (RXFILTERED)1105.49.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)1115.49.13 Receive Octet Frames Register (RXOCTETS)1115.49.14 Good Transmit Frames Register (TXGOODFRAMES)1115.49.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)1125.49.16 Multicast Transmit Frames Register (TXMCASTFRAMES)1125.49.17 Pause Transmit Frames Register (TXPAUSEFRAMES)1125.49.18 Deferred Transmit Frames Register (TXDEFERRED)1125.49.19 Transmit Collision Frames Register (TXCOLLISION)1125.49.20 Transmit Single Collision Frames Register (TXSINGLECOLL)1135.49.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)1135.49.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL)1135.49.23 Transmit Late Collision Frames Register (TXLATECOLL)1135.49.24 Transmit Underrun Error Register (TXUNDERRUN)1135.49.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)1145.49.26 Transmit Octet Frames Register (TXOCTETS)1145.49.27 Transmit and Receive 64 Octet Frames Register (FRAME64)1145.49.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127)1145.49.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255)1145.49.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)1155.49.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)1155.49.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)1155.49.33 Network Octet Frames Register (NETOCTETS)1155.49.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)1165.49.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS)1165.49.36 Receive DMA Overruns Register (RXDMAOVERRUNS)116Appendix A Glossary117Appendix B Revision History119文件大小: 925.2 KB页数: 120Language: English打开用户手册