Intel D425 AU80610006252AA 用户手册
产品代码
AU80610006252AA
Processor Configuration Registers
74
Datasheet
Bit Access Default
Value
RST/
PWR
Description
12:9 RW
0h Core
ALLPRE to ACT Delay
(C0sd0_cr_preall_act):
From the launch of a precharged command
wait for these many # of MCLKs before
launching a activate command. Corresponds to
tPALL_RP.
(C0sd0_cr_preall_act):
From the launch of a precharged command
wait for these many # of MCLKs before
launching a activate command. Corresponds to
tPALL_RP.
8:0 RW
00000000
0b
Core
REF to ACT Delayed (C0sd_cr_rfsh_act):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between REF and ACT commands to the same
rank. Corresponds to tRFC at DDR Spec.
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between REF and ACT commands to the same
rank. Corresponds to tRFC at DDR Spec.
1.6.10
C0CYCTRKWR - Channel 0 CYCTRK WR
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
256-257h
Default Value:
0000h
Access:
RW;
Size: 16
bits
Channel 0 CYCTRK WR Registers.
Bit Acces
s
Defau
lt
Value
RST/
PWR
Description
15:12 RW 0h Core
ACT To Write Delay (C0sd_cr_act_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the ACT
and WRITE commands to the same rank-
bank. Corresponds to tRCD_wr at DDR Spec.
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the ACT
and WRITE commands to the same rank-
bank. Corresponds to tRCD_wr at DDR Spec.
11:8 RW 0h Core
Same Rank Write To Write Delayed
(C0sd_cr_wrsr_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two
WRITE commands to the same rank.
(C0sd_cr_wrsr_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two
WRITE commands to the same rank.
7:4 RW 0h Core
Different Rank Write to Write Delay
(C0sd_cr_wrdr_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two
WRITE commands to different ranks. Corresponds
(C0sd_cr_wrdr_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between two
WRITE commands to different ranks. Corresponds
to tWR_WR at DDR Spec.
3:0 RW 0h Core
READ To WRTE Delay (C0sd_cr_rd_wr):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the READ
and WRITE commands. Corresponds to tRD_WR.
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between the READ
and WRITE commands. Corresponds to tRD_WR.