Intel 2 Duo T7200 LE80537GF0414M 用户手册
产品代码
LE80537GF0414M
Summary Tables of Changes
36
Specification Update
Errata for Intel
®
Celeron
®
Processor 500 Series for Platforms Based
on Mobile Intel
®
965 Express Chipset Family
Number
Stepping Stepping Stepping
Plans
Errata
A-1
E-1
M-1
AH1
X
X
X
No Fix Writing the Local Vector Table (LVT) When an Interrupt Is
Pending May Cause an Unexpected Interrupt
AH2
X
X
X
No Fix LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly Deassert
AR3
No Fix Erratum Removed
AH4
X
X
X
No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
AH5
X
X
X
No Fix DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
Count for Saturating SIMD Instructions Retired (Event CFH)
AH6
X
Fixed SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
AH7
X
X
X
No Fix General Protection Fault (#GP) for Instructions Greater than 15
Bytes May Be Preempted
AH8
X
X
X
No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
AH9
X
X
X
No Fix The Processor May Report a #TS Instead of a #GP Fault
AH11
X
X
X
No Fix A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AH12
X
X
X
No Fix Programming the Digital Thermal Sensor (DTS) Threshold May
Cause Unexpected Thermal Interrupts
AH13
X
X
X
No Fix Count Value for Performance-Monitoring Counter
PMH_PAGE_WALK May Be Incorrect
AH14
X
X
X
No Fix LER MSRs May Be Incorrectly Updated
AH15
X
X
X
No Fix Performance Monitoring Events for Retired Instructions (C0H)
May Not Be Accurate
AH16
X
X
X
No Fix Performance Monitoring Event For Number Of Reference Cycles
When The Processor Is Not Halted (3CH) Does Not Count
According To The Specification
According To The Specification
AR16
X
Fixed Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AH18
X
X
X
No Fix Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering
Issue
Issue
AH19
X
X
X
No Fix Code Segment Limit Violation May Occur On 4 Gigabyte Limit
Check
AH20
x
Fixed FP Inexact-Result Exception Flag May Not Be Set