Intel QX9775 EU80574XL088N 数据表

65

AP[1:0]#

I/O

AP[1:0]# (Address Parity) are driven by the request 
initiator along with ADS#, A[37:3]#, and the transaction 
type on the REQ[4:0]# signals. A correct parity signal is 
high if an even number of covered signals are low and low 
if an odd number of covered signals are low. This allows 
parity to be high when all the covered signals are high. 
AP[1:0]# must be connected to the appropriate pins of all 
processor FSB agents. The following table defines the 
coverage model of these signals.

3

BCLK[1:0]

I

The differential bus clock pair BCLK[1:0] (Bus Clock) 
determines the FSB frequency. All processor FSB agents 
must receive these signals to drive their outputs and latch 
their inputs.
All external timing parameters are specified with respect 
to the rising edge of BCLK0 crossing V

CROSS

.

3

BINIT#

I/O

BINIT# (Bus Initialization) may be observed and driven 
by all processor FSB agents and if used, must connect the 
appropriate pins of all such agents. If the BINIT# driver is 
enabled during power on configuration, BINIT# is 
asserted to signal any bus condition that prevents reliable 
future operation.
If BINIT# observation is enabled during power-on 
configuration (see 

) and BINIT# is sampled 

asserted, symmetric agents reset their bus LOCK# 
activity and bus request arbitration state machines. The 
bus agents do not reset their I/O Queue (IOQ) and 
transaction tracking state machines upon observation of 
BINIT# assertion. Once the BINIT# assertion has been 
observed, the bus agents will re-arbitrate for the FSB and 
attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on 
configuration, a priority agent may handle an assertion of 
BINIT# as appropriate to the error handling architecture 
of the system.

3

BNR#

I/O

BNR# (Block Next Request) is used to assert a bus stall 
by any bus agent who is unable to accept new bus 
transactions. During a bus stall, the current bus owner 
cannot issue any new transactions.
Since multiple agents might need to request a bus stall at 
the same time, BNR# is a wired-OR signal which must 
connect the appropriate pins of all processor FSB agents. 
In order to avoid wired-OR glitches associated with 
simultaneous edge transitions driven by multiple drivers, 
BNR# is activated on specific clock edges and sampled on 
specific clock edges.

3

A[37:24]#

AP0#

AP1#

A[23:3]#

AP1#

AP0#

REQ[4:0]#

AP1#

AP0#