用户手册 — Intel QX9775

目录

• Intel® Core™2 Extreme Processor QX9775

  1
  • Contents

    3
    • Figures

      4
    • Tables

      4
  • Revision History

    5
  • Intel® Core™2 Extreme Processor QX9775 Features

    7
• 1 Introduction

  9
  • 1.1 Terminology

    10
  • 1.2 References

    12
• 2 Electrical Specifications

  13
  • 2.1 Front Side Bus and GTLREF

    13
  • 2.2 Power and Ground Lands

    13
  • 2.3 Decoupling Guidelines

    14
    • 2.3.1 VCC Decoupling

      14
    • 2.3.2 VTT Decoupling

      14
    • 2.3.3 Front Side Bus AGTL+ Decoupling

      14
  • 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

    15
    • Table 2-1. Core Frequency to FSB Multiplier Configuration

      15
    • 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])

      16
      • Table 2-2. BSEL[2:0] Frequency Table

        16
    • 2.4.2 PLL Power Supply

      16
  • 2.5 Voltage Identification (VID)

    17
    • Table 2-3. Voltage Identification Definition

      18
    • Table 2-4. Loadline Selection Truth Table for LL_ID[1:0]

      19
    • Table 2-5. Market Segment Selection Truth Table for MS_ID[1:0]

      19
  • 2.6 Reserved, Unused, and Test Signals

    19
  • 2.7 Front Side Bus Signal Groups

    20
    • Table 2-6. FSB Signal Groups (Sheet 1 of 2)

      20
    • Table 2-7. AGTL+ Signal Description Table

      21
    • Table 2-8. Non AGTL+ Signal Description Table

      21
    • Table 2-9. Signal Reference Voltages

      22
  • 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals

    22
  • 2.9 Test Access Port (TAP) Connection

    22
  • 2.10 Platform Environmental Control Interface (PECI) DC Specifications

    22
    • 2.10.1 DC Characteristics

      22
      • Table 2-10. PECI DC Electrical Limits

        23
    • 2.10.2 Input Device Hysteresis

      23
      • Figure 2-1. Input Device Hysteresis

        23
  • 2.11 Mixing Processors

    24
  • 2.12 Absolute Maximum and Minimum Ratings

    24
    • Table 2-11. Processor Absolute Maximum Ratings

      25
  • 2.13 Processor DC Specifications

    25
    • Table 2-12. Voltage and Current Specifications

      26
    • Figure 2-2. Processor Load Current versus Time

      27
    • Table 2-13. Processor VCC Static and Transient Tolerance

      28
    • Figure 2-3. Processor VCC Static and Transient Tolerance Load Lines

      29
    • Table 2-14. AGTL+ Signal Group DC Specifications

      29
    • Table 2-15. CMOS Signal Input/Output Group and TAP Signal Group DC Specifications

      30
    • Table 2-16. Open Drain Output Signal Group DC Specifications

      30
    • 2.13.1 VCC Overshoot Specification

      30
      • Table 2-17. VCC Overshoot Specifications

        30
      • Figure 2-4. VCC Overshoot Example Waveform

        31
    • 2.13.2 Die Voltage Validation

      31
  • 2.14 AGTL+ FSB Specifications

    32
    • Table 2-18. AGTL+ Bus Voltage Definitions

      32
    • Table 2-19. FSB Differential BCLK Specifications

      33
    • Figure 2-5. Differential Clock Waveform

      34
    • Figure 2-6. Differential Clock Crosspoint Specification

      34
    • Figure 2-7. Differential Rising and Falling Edge Rates

      34
• 3 Mechanical Specifications

  35
  • Figure 3-1. Processor Package Assembly Sketch

    35
  • 3.1 Package Mechanical Drawings

    35
    • Figure 3-2. Processor Package Drawing (Sheet 1 of 3)

      36
    • Figure 3-3. Processor Package Drawing (Sheet 2 of 3)

      37
    • Figure 3-4. Processor Package Drawing (Sheet 3 of 3)

      38
  • 3.2 Processor Component Keepout Zones

    39
  • 3.3 Package Loading Specifications

    39
    • Table 3-1. Package Loading Specifications

      39
  • 3.4 Package Handling Guidelines

    40
    • Table 3-2. Package Handling Guidelines

      40
  • 3.5 Package Insertion Specifications

    40
  • 3.6 Processor Mass Specifications

    40
  • 3.7 Processor Materials

    40
    • Table 3-3. Processor Materials

      40
  • 3.8 Processor Markings

    41
    • Figure 3-5. Processor Top-side Markings (Example)

      41
  • 3.9 Processor Land Coordinates

    42
    • Figure 3-6. Processor Land Coordinates, Top View

      42
    • Figure 3-7. Processor Land Coordinates, Bottom View

      43
• 4 Land Listing and Signal Description

  45
  • 4.1 Land Listing

    45
    • Table 4-1. Land Listing by Land Name (Sheet 1 of 17)

      46
    • Table 4-2. Land Listing by Land Number (Sheet 1 of 17)

      55
  • 4.2 Signal Definitions

    64
    • Table 4-1. Signal Definitions (Sheet 1 of 11)

      64
• 5 Thermal Specifications

  75
  • 5.1 Package Thermal Specifications

    75
    • 5.1.1 Thermal Specifications

      75
      • Table 5-1. Processor Thermal Specifications

        76
      • Figure 5-1. Processor Thermal Profile

        76
      • Table 5-2. Processor Thermal Profile Table

        77
    • 5.1.2 Thermal Metrology

      77
      • Figure 5-2. Case Temperature (TCASE) Measurement Location

        78
  • 5.2 Processor Thermal Features

    78
    • 5.2.1 Intel® Thermal Monitor Features

      78
      • 5.2.1.1 Thermal Monitor (TM1)

        78
      • 5.2.1.2 Enhanced Thermal Monitor (TM2)

        79
        • Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering

          80
    • 5.2.2 On-Demand Mode

      80
    • 5.2.3 PROCHOT# Signal

      80
    • 5.2.4 FORCEPR# Signal

      81
    • 5.2.5 THERMTRIP# Signal

      81
  • 5.3 Platform Environment Control Interface (PECI)

    81
    • 5.3.1 Introduction

      81
      • Figure 5-4. Processor PECI Topology

        82
      • 5.3.1.1 TCONTROL and TCC Activation on PECI-based Systems

        83
        • Figure 5-5. Conceptual Fan Control Diagram of PECI-based Platforms

          83
      • 5.3.1.2 Processor Thermal Data Sample Rate and Filtering

        83
    • 5.3.2 PECI Specifications

      84
      • 5.3.2.1 PECI Device Address

        84
      • 5.3.2.2 PECI Command Support

        84
      • 5.3.2.3 PECI Fault Handling Requirements

        84
      • 5.3.2.4 PECI GetTemp0()and GetTemp1() Error Code Support

        84
        • Table 5-3. GetTemp0() GetTemp1()Error Codes

          84
• 6 Features

  85
  • 6.1 Power-On Configuration Options

    85
    • Table 6-1. Power-On Configuration Option Lands

      85
  • 6.2 Clock Control and Low Power States

    85
    • Figure 6-1. Stop Clock State Machine

      86
    • 6.2.1 Normal State

      86
    • 6.2.2 HALT or Extended HALT State

      86
      • 6.2.2.1 HALT State

        86
      • 6.2.2.2 Extended HALT State

        87
        • Table 6-2. Extended HALT Maximum Power

          87
    • 6.2.3 Stop-Grant State

      87
    • 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State

      88
      • 6.2.4.1 HALT Snoop State, Stop Grant Snoop State

        88
      • 6.2.4.2 Extended HALT Snoop State

        88
  • 6.3 Enhanced Intel SpeedStep® Technology

    89