Intel QX9775 EU80574XL088N 数据表
产品代码
EU80574XL088N
Features
86
Datasheet
6.2.1
Normal State
This is the normal operating state for the processor.
6.2.2
HALT or Extended HALT State
The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state
must be enabled for the processor to remain within its specifications. The
Extended HALT state requires support for dynamic VID transitions in the platform.
6.2.2.1
HALT State
HALT is a low power state entered when the processor have executed the HALT or
MWAIT instruction. When one of the processor cores execute the HALT or MWAIT
instruction, that processor core is halted; however, the other processor continues
normal operation. The processor will transition to the Normal state upon the occurrence
of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the
front side bus. RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT state. See the Intel
®
64 and IA-32 Architecture Software
Developer's Manual.
Figure 6-1. Stop Clock State Machine
Extended HALT or HALT State
BCLK running
Snoops and interrupts allowed
Snoops and interrupts allowed
Normal State
Normal execution
Extended HALT Snoop or HALT
Snoop State
Snoop State
BCLK running
Service snoops to caches
Service snoops to caches
Stop Grant State
BCLK running
Snoops and interrupts allowed
Snoops and interrupts allowed
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
RESET#, FSB interrupts
STPCLK#
Asserted
Asserted
STPCLK#
De-asserted
De-asserted
S
TP
C
LK
#
A
ss
er
te
d
S
TP
C
LK
#
D
e-
as
se
rte
d
Snoop Event Occurs
Snoop Event Serviced
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
HALT Bus Cycle Generated
Stop Grant Snoop State
BCLK running
Service snoops to caches
Service snoops to caches