Intel QX9775 EU80574XL088N 数据表
产品代码
EU80574XL088N
Datasheet
27
Electrical Specifications
8.
Minimum V
CC
and maximum I
CC
are specified at the maximum processor case temperature
.
9.
This specification refers to the total reduction of the load line due to VID transitions below
the specified VID.
the specified VID.
10.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same frequency may have different VID settings.
devices at the same frequency may have different VID settings.
11.
This specification applies to the VCCPLL land.
12.
Baseboard bandwidth is limited to 20 MHz.
13.
I
CC_TDC
is the sustained (DC equivalent) current that the processor is capable of drawing
indefinitely and should be used for the voltage regulator temperature assessment. The
voltage regulator is responsible for monitoring its temperature and asserting the necessary
signal to inform the processor of a thermal excursion. The processor is capable of drawing
I
voltage regulator is responsible for monitoring its temperature and asserting the necessary
signal to inform the processor of a thermal excursion. The processor is capable of drawing
I
CC_TDC
indefinitely. Refer to
for further details on the average processor current
draw over various time durations. This parameter is based on design characterization and
is not tested.
is not tested.
14.
This is the maximum total current drawn from the V
TT
plane by only one processor with R
TT
enabled. This specification does not include the current coming from on-board termination
(R
(R
TT
), through the signal line. Refer to the Voltage Regulator Design Guidelines to
determine the total I
TT
drawn by the system. This parameter is based on design
characterization and is not tested.
15.
I
CC
_
VTT
_
OUT
is specified at 1.1 V.
16.
I
CC_RESET
is specified while PWRGOOD and RESET# are asserted.
17.
The processor is intended for dual processor workstations only.
.
NOTES:
1.
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents
greater than I
greater than I
CC_TDC
.
2.
Not 100% tested. Specified by design characterization.
Figure 2-2. Processor Load Current versus Time
12 0
12 5
13 0
13 5
14 0
14 5
15 0
15 5
16 0
0 . 0 1
0 . 1
1
10
10 0
10 0 0
Tim e Duration (s )
S
u
s
ta
ine
d C
u
rr
e
n
t (A
)