National Instruments 5441 用户手册

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Sample Clock 
Source

Sample Rate Range

Sample Rate Resolution

—

Divide-by-N

23.84 S/s to 100 MS/s

Settable to (100 MS/s) / N
(1 

≤ N ≤ 4,194,304)

High 
Resolution

10 S/s to 100 MS/s

1.06 µHz

CLK IN

200 kS/s to 105 MS/s

Resolution determined by 
external clock source.

External Sample Clock duty 
cycle tolerance 40% to 60%.

DDC CLK IN

10 S/s to 105 MS/s

PXI Star 
Trigger

10 S/s to 105 MS/s

PXI_Trig<0..7>

10 S/s to 20 MS/s

Sample Rate 

(MS/s)

DAC

Interpolation 

Factor

Effective Sample 

Rate

DAC Effective 
Sample Rate = 
(DAC 
Interpolation 
Factor) 

× 

(Sample Rate)

Refer to the 

section for OSP 
Interpolation.

10 S/s to 

105 MS/s

1 (Off)

10 S/s to 

105 MS/s

12.5 MS/s to 

105 MS/s

2

25 MS/s to 

210 MS/s

10 MS/s to 

100 MS/s

4

40 MS/s to 

400 MS/s

10 MS/s to 

50 MS/s

8

80 MS/s to 

400 MS/s

Sample Clock 
Source

Delay Adjustment Range

Delay Adjustment 

Resolution

—

Divide-by-N

±1 sample clock period

<10 ps

High-
Resolution

±1 sample clock period

Sample Clock 
Period/16,384

External (all)

 0 ns to 7.6 ns

<15 ps