National Instruments 5441 用户手册

Sample Clock 
Source

System Phase Noise 

Density

(dBc/Hz) Offset

System Output Jitter

(Integrated from 

100 Hz to 100 kHz)

1. High-

Resolution 
specifications 
increase as the 
Sample Rate is 
decreased.

2. PXI Star 

trigger 
specification 
is valid when 
the Sample 
Clock Source 
is locked to 
PXI_CLK10.

100 Hz

1 kHz

10 kHz

Divide-by-N

–110

–131

–137

<1.0 ps rms

High-
Resolution

1

–114

–126

–126

<4.0 ps rms

CLK IN

–113

–132

–135

<1.1 ps rms

PXI Star 
Trigger

2

–115

–118

–130

<3.0 ps rms

External 
Sample Clock 
Input Jitter 
Tolerance

Cycle-Cycle Jitter 

±300 ps

Period Jitter 

±1 ns

—

Exported 
Sample Clock 
Destinations

1. PFI<0..1> (SMB front panel connectors)

2. DDC CLK OUT (DIGITAL DATA & CONTROL front 

panel connector)

3. PXI_Trig<0..7> (backplane connector) 

Exported Sample 
Clocks can be 
divided by integer 
K (1 

≤ K ≤ 

4,194,304).

Exported 
Sample Clock 
Destinations

Maximum 
Frequency

Jitter (Typical)

Duty Cycle

—

PFI<0..1>

105 MHz

PFI 0: 6 ps rms

PFI 1: 12 ps rms 

25% to 65%

DDC CLK 
OUT

105 MHz

40 ps rms

40% to 60%

PXI_Trig<0..7>

20 MHz

—

—