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页码 113
Glossary
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 National Instruments Corporation
G-5
system memory. Programming the DMA controller and servicing 
interrupts can take several milliseconds in some cases. During this 
time, data accumulates in the FIFO for future retrieval. With a 
larger FIFO, longer latencies can be tolerated. In the case of analog 
output, a FIFO permits faster update rates, because the waveform 
data can be stored in the FIFO ahead of time. This again reduces the 
effect of latencies associated with getting the data from system 
memory to the DAQ device.
FREQ_OUT
frequency output signal
ft
feet
G
GATE
gate signal
GPCTR
general-purpose counter signal
GPCTR0_GATE
general-purpose counter 0 gate signal
GPCTR0_OUT
general-purpose counter 0 output signal
GPCTR0_SOURCE
general-purpose counter 0 clock source signal
GPCTR0_UP_DOWN
general-purpose counter 0 up down signal
GPCTR1_GATE
general-purpose counter 1 gate signal
GPCTR1_OUT
general-purpose counter 1 output signal
GPCTR1_SOURCE
general-purpose counter 1 clock source signal
GPCTR1_UP_DOWN
general-purpose counter 1 up down signal
H
h
hour
hex
hexadecimal
Hz
hertz
PCI_E.book  Page 5  Thursday, June 25, 1998  12:55 PM