Intel architecture ia-32 用户手册

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页码 636
3-44 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
If the execute disable bit is enabled in an IA-32 processor, the reserved bits in paging data struc-
tures for legacy 32-bit mode and 64-bit mode are shown in Table 3-5.
Table 3-4.  Reserved Bit Checking When Execute Disable Bit is Disabled
Mode
Paging Mode
Paging Structure
Check Bits
32-bit
4-KByte pages (PAE = 0, PSE = 0)
PDE and PT
No reserved bits checked
4-MByte page (PAE = 0, PSE = 1)
PDE
Bit [21] 
4-KByte page (PAE = 0, PSE = 1)
PDE
No reserved bits checked
4-KByte and 4-MByte page (PAE = 
0, PSE = 1)
PTE
No reserved bits checked
4-KByte and 2-MByte pages (PAE 
= 1, PSE = x)
PDP table entry
Bits [63:40] & [8:5] & [2:1] 
2-MByte page (PAE = 1, PSE = x)
 PDE
Bits [63:40] & [20:13] 
4-KByte pages (PAE =1, PSE = x)
PDE
Bits [63:40] 
4-KByte and 2-MByte pages (PAE 
= 1, PSE = x)
PTE
Bits [63:40] 
64-bit
4-KByte and 2-MByte pages (PAE 
= 1, PSE = x)
PML4E
Bit [63], bits [51:40] 
4-KByte and 2-MByte pages (PAE 
= 1, PSE = x)
PDPTE
Bit [63], bits [51:40] 
2-MByte page (PAE =1, PSE = x)
PDE, 2-MByte page
Bit [63], bits [51:40] & [20:13] 
4-KByte pages (PAE = 1, PSE = x)
PDE, 4-KByte page
Bit [63], bits [51:40] 
4-KByte and 2-MByte pages (PAE 
= 1, PSE = x)
PTE
Bit [63], bits [51:40] 
Table 3-5.  Reserved Bit Checking When Execute Disable Bit is Enabled
Mode
Paging Mode
Paging Structure
Check Bits
32-bit
 4-KByte pages (PAE = 0, PSE = 
0)
PDE and PT
No reserved bits checked
4-MByte page (PAE = 0, PSE = 1)
PDE
Bit [21] 
4-KByte page (PAE = 0, PSE = 1)
PDE
No reserved bits checked
4-KByte and 4-MByte page (PAE = 
0, PSE = 1)
PTE
No reserved bits checked
4-KByte and 2-MByte pages (PAE 
= 1, PSE = x)
PDP table entry
Bits [63:40] & [8:5] & [2:1] 
2-MByte page (PAE = 1, PSE = x)
PDE
Bits [63:40] & [20:13] 
4-KByte pages (PAE = 1, PSE = x)
PDE
Bits [63:40] 
4-KByte and 2-MByte pages (PAE 
= 1, PSE = x)
PTE
Bits [63:40]