Intel Pentium M 730 RH80536GE0252M 用户手册

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 4 Processor-M Datasheet  

87

SKTOCC#

Output

SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System 
board designers may use this pin to determine if the processor is present.

SLP#

Input

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the 
Sleep state. During Sleep state, the processor stops providing internal clock signals 
to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in 
this state will not recognize snoops or interrupts. The processor will only recognize 
the assertion of the RESET# signal, deassertion of SLP#, and assertion of DPSLP# 
input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state 
and returns to Stop-Grant state, restarting its internal clock signals to the bus and 
processor core units. If the BCLK input is stopped or if DPSLP# is asserted while in 
the Sleep state, the processor will exit the Sleep state and transition to the Deep 
Sleep state.

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously by system logic. 
On accepting a System Management Interrupt, the processor saves the current 
state and enter System Management Mode (SMM). An SMI Acknowledge 
transaction is issued, and the processor begins program execution from the SMM 
handler.

If SMI# is asserted during the deassertion of RESET# the processor will tristate its 
outputs.

STPCLK#

Input

Assertion of STPCLK# (Stop Clock) causes the processor to enter a low power 
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and 
stops providing internal clock signals to all processor core units except the system 
bus and APIC units. The processor continues to snoop bus transactions and 
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the 
processor restarts its internal clock to all units and resumes execution. The 
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an 
asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor Test Bus (also known 
as the Test Access Port).

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the 
serial input needed for JTAG specification support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides 
the serial output needed for JTAG specification support.

TESTHI[10:8]

TESTHI[5:0]

Input

TESTHI[10:8] and TESTHI[5:0] must be connected to a V

CC

 power source through 

a resistor for proper processor operation. See 

 for more details.

THERMDA

Other

Thermal Diode Anode. See Section 6. 

THERMDC

Other

Thermal Diode Cathode. See Section 6.