Intel III 450 MHz 80525PY450512 数据表
产品代码
80525PY450512
32
Datasheet
Electrical Specifications
2.12
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to V
resistors to V
TT
at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the V
TT
voltage supply and generally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called V
buffers using a reference voltage called V
REF
.
lists the nominal specification for the AGTL+ termination voltage (V
TT
). The AGTL+
reference voltage (V
REF
) is generated on the processor substrate for the processor core, but should
be set to 2/3 V
TT
for other AGTL+ logic using a voltage divider on the baseboard. It is important
that the baseboard impedance be specified and held to a ±15% tolerance, and that the intrinsic trace
capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on
the GTL+ buffer specification, see the Intel
capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on
the GTL+ buffer specification, see the Intel
®
Pentium
®
II Processor Developer's Manual
(Document Number 243502) and AP-585, Intel
®
Pentium
®
II Processor GTL+ Guidelines
(Document Number 243330).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Pentium III processors contain AGTL+ termination resistors at the end of each signal trace on the processor
2. Pentium III processors contain AGTL+ termination resistors at the end of each signal trace on the processor
substrate. Pentium III processors generate V
REF
on the processor substrate by using a voltage divider on
V
TT
supplied through the SC 242 connector.
3. V
TT
must be held to 1.5 V ±9%; dI
CCVTT
/dt is specified in
. It is recommended that V
TT
be held to
1.5 V ±3% while the Pentium III processor system bus is idle. This is measured at the processor edge
fingers.
fingers.
4. R
TT
must be held within a tolerance of ±5%
5. V
REF
is generated on the processor substrate to be 2/3 V
TT
±2% nominally.
2.13
System Bus AC Specifications
The Pentium III processor system bus timings specified in this section are defined at the Pentium III
processor core pads. Unless otherwise specified, timings are tested at the processor core during
manufacturing. See
processor core pads. Unless otherwise specified, timings are tested at the processor core during
manufacturing. See
for the Pentium III processor edge connector signal definitions. See
for the Pentium III processor closest accessible core pad to substrate via assignment.
through
list the AC specifications associated with the Pentium III processor
through
contain the system bus clock core frequency and cache bus frequencies,
contains
the AGTL+ specifications,
contains the CMOS signal group specifications,
contains timings for the Reset conditions,
covers APIC bus timing, and
covers
TAP timing.
All Pentium II processor system bus AC specifications for the AGTL+ signal group are relative to
the rising edge of the BCLK input. All AGTL+ timings are referenced to V
the rising edge of the BCLK input. All AGTL+ timings are referenced to V
REF
for both ‘0’ and ‘1’
logic levels unless otherwise specified.
Table 11. AGTL+ Bus Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
1, 2
V
TT
Bus Termination Voltage
1.365
1.50
1.635
V
3
R
TT
Termination Resistor
56
Ω
4
V
REF
Bus Reference Voltage
0.95
2/3 V
TT
1.05
V
5