用户手册 — Intel III 450 MHz

目录

• Title Page

  1
• Contents

  3
• Revision History

  8
• 1.0 Introduction

  9
  • 1.1 Terminology

    10
    • 1.1.1 S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology

      10
    • 1.1.2 Processor Naming Convention

      11
  • 1.2 Related Documents

    12
• 2.0 Electrical Specifications

  13
  • 2.1 Processor System Bus and VREF

    13
  • 2.2 Clock Control and Low Power States

    14
    • 2.2.1 Normal State—State 1

      15
    • 2.2.2 AutoHALT Powerdown State—State 2

      15
    • 2.2.3 Stop-Grant State—State 3

      15
    • 2.2.4 HALT/Grant Snoop State—State 4

      16
    • 2.2.5 Sleep State—State 5

      16
    • 2.2.6 Deep Sleep State—State 6

      16
    • 2.2.7 Clock Control

      17
  • 2.3 Power and Ground Pins

    17
  • 2.4 Decoupling Guidelines

    17
    • 2.4.1 Processor VCCCORE Decoupling

      18
    • 2.4.2 Processor System Bus AGTL+ Decoupling

      18
  • 2.5 Processor System Bus Clock and Processor Clocking

    18
  • 2.6 Voltage Identification

    18
  • 2.7 Processor System Bus Unused Pins

    20
  • 2.8 Processor System Bus Signal Groups

    20
    • 2.8.1 Asynchronous vs. Synchronous for System Bus Signals

      21
    • 2.8.2 System Bus Frequency Select Signal (BSEL0)

      22
  • 2.9 Test Access Port (TAP) Connection

    23
  • 2.10 Maximum Ratings

    24
  • 2.11 Processor DC Specifications

    25
  • 2.12 AGTL+ System Bus Specifications

    32
  • 2.13 System Bus AC Specifications

    32
• 3.0 Signal Quality Specifications

  40
  • 3.1 BCLK, PICCLK, and PWRGOOD Signal Quality Specifications and Measurement Guidelines

    40
  • 3.2 AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and Measurement Guidelines

    41
    • 3.2.1 Overshoot/Undershoot Magnitude

      41
    • 3.2.2 Overshoot/Undershoot Pulse Duration

      42
    • 3.2.3 Overshoot/Undershoot Activity Factor

      42
    • 3.2.4 Reading Overshoot/Undershoot Specification Tables

      43
    • 3.2.5 Determining If a System Meets the Overshoot/Undershoot Specifications

      44
  • 3.3 AGTL+ and Non-AGTL+ Ringback Specifications and Measurement Guidelines

    46
    • 3.3.1 Settling Limit Guideline

      48
• 4.0 Thermal Specifications and Design Considerations

  49
  • 4.1 Thermal Specifications

    50
    • 4.1.1 Thermal Diode

      53
• 5.0 S.E.C.C. and S.E.C.C.2 Mechanical Specifications

  54
  • 5.1 S.E.C.C. Mechanical Specifications

    54
  • 5.2 S.E.C.C.2 Mechanical Specification

    61
  • 5.3 S.E.C.C.2 Structural Mechanical Specification

    67
  • 5.4 Processor Package Materials Information

    69
  • 5.5 Intel® Pentium® III Processor Signal Listing

    69
  • 5.6 Intel® Pentium® III Processor Core Pad to Substrate Via Assignments

    76
    • 5.6.1 Processor Core Pad Via Assignments (CPUID=067xh)

      76
    • 5.6.2 Processor Core Signal Assignments (CPUID=067xh)

      76
    • 5.6.3 Processor Core Pad Via Assignments (CPUID=068xh)

      87
• 6.0 Boxed Processor Specifications

  88
  • 6.1 Introduction

    88
  • 6.2 Fan Heatsink Mechanical Specifications

    88
    • 6.2.1 Intel® Boxed Processor Fan Heatsink Dimensions

      88
    • 6.2.2 Intel® Boxed Processor Fan Heatsink Weight

      90
    • 6.2.3 Intel® Boxed Processor Retention Mechanism

      90
  • 6.3 Fan Heatsink Electrical Requirements

    91
    • 6.3.1 Fan Heatsink Power Supply

      91
  • 6.4 Fan Heatsink Thermal Specifications

    92
    • 6.4.1 Intel® Boxed Processor Cooling Requirements

      92
• 7.0 Intel® Pentium® III Processor Signal Description

  93
  • 7.1 Alphabetical Signals Reference

    93
  • 7.2 Signal Summaries

    100