Intel i7-3920XM Extreme AW8063801009607 用户手册
产品代码
AW8063801009607
Processor Configuration Registers
246
Datasheet, Volume 2
2.14.2
TC_RAP_C1—Timing of DDR – Regular Access Parameters
Register
This register provides the regular timing parameters in DCLK cycles.
11:8
RW-L
6h
Uncore
CAS latency in DCLK cycles (tCL)
Delay from CAS command to data out of DDR pins. This does not
Delay from CAS command to data out of DDR pins. This does not
define the sample point in the I/O. This is defined by training in
round-trip register and other registers, because this is also
affected by board delays
Delay from CAS command to data out of DDR pins. Range is 5–
Delay from CAS command to data out of DDR pins. Range is 5–
15.
Note:
This does not define the sample point in the IO. This is
defined by training in round-trip register and other
registers, because this is also affected by board delays.
Note:
The range of 12–15 is not yet defined by JEDEC, will be
tested only when such definition will exist.
7:4
RW-L
6h
Uncore
tRP in DCLK cycles (tRP)
PRE to ACT same bank delay range is 4–15 DCLK cycles
PRE to ACT same bank delay range is 4–15 DCLK cycles
3:0
RW-L
6h
Uncore
tRCD in DCLK cycles (tRCD)
ACT to CAS (RD or WR) same bank delay tRCD range is between
ACT to CAS (RD or WR) same bank delay tRCD range is between
4 and 15.
B/D/F/Type:
0/0/0/MCHBAR MC1
Address Offset:
4400–4403h
Reset Value:
00146666h
Access:
RW-L
Size:
32 bits
BIOS Optimal Default
00h
Bit
Access
Reset
Value
RST/
PWR
Description
B/D/F/Type:
0/0/0/MCHBAR MC1
Address Offset:
4404–4407h
Reset Value:
86104344h
Access:
RW-L
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:30
RW-L
10b
Uncore
1n 2N or 3N selection (CMD_stretch)
This field defines the operation mode of the command
00 = 1N operation
10 = 2N operation
11 = 3N operation
This field defines the operation mode of the command
00 = 1N operation
10 = 2N operation
11 = 3N operation
29
RW-L
0b
Uncore
Command 3-state options (CMD_3st)
This bit defines when command & address bus is driving.
0 = Drive when channel is active. Tri-stated when all ranks are in
This bit defines when command & address bus is driving.
0 = Drive when channel is active. Tri-stated when all ranks are in
CKE-off or when memory is in SR or deeper.
1 = Command bus is always driving. When no new valid
command is driven, previous command & address is driven
28:24
RW-L
06h
Uncore
tWR in DCLK cycles (tWR)
Write recovery time. The range is 5 to 16 DCLK cycles.
Write recovery time. The range is 5 to 16 DCLK cycles.
23:16
RW-L
10h
Uncore
tFAW in DCLK cycles (tFAW)
Four-activate window is the time frame in which maximum of 4
Four-activate window is the time frame in which maximum of 4
ACT commands to the same rank are allowed. The minimum
value is 4*tRRD, whereas the maximum value is 63 DCLK cycles.