用户手册 (AW8063801009607)目录1 Introduction132 Processor Configuration Registers152.1 Register Terminology152.2 PCI Devices and Functions162.3 System Address Map172.3.1 Legacy Address Range192.3.1.1 DOS Range (0h–9_FFFFh)202.3.1.2 Legacy Video Area (A_0000h–B_FFFFh)202.3.1.3 PAM (C_0000h–F_FFFFh)212.3.2 Main Memory Address Range (1 MB – TOLUD)222.3.2.1 ISA Hole (15 MB – 16 MB)222.3.2.2 TSEG232.3.2.3 Protected Memory Range (PMR) – (programmable)232.3.2.4 DRAM Protected Range (DPR)242.3.2.5 Pre-allocated Memory242.3.2.6 Graphics Stolen Spaces242.3.2.7 Intel® Management Engine (Intel® ME) UMA252.3.3 PCI Memory Address Range (TOLUD – 4 GB)252.3.3.1 APIC Configuration Space (FEC0_0000h – FECF_FFFFh)262.3.3.2 HSEG (FEDA_0000h – FEDB_FFFFh)272.3.3.3 MSI Interrupt Memory Space (FEE0_0000 – FEEF_FFFF)272.3.3.4 High BIOS Area272.3.4 Main Memory Address Space (4 GB to TOUUD)272.3.4.1 Memory Re-claim Background282.3.4.2 Indirect Accesses to MCHBAR Registers292.3.4.3 Memory Remapping292.3.4.4 Hardware Remap Algorithm292.3.4.5 Programming Model302.3.5 PCI Express* Configuration Address Space352.3.6 PCI Express* Graphics Attach (PEG)352.3.7 Graphics Memory Address Ranges362.3.7.1 IOBAR Mapped Access to Device 2 MMIO Space362.3.7.2 Trusted Graphics Ranges362.3.8 System Management Mode (SMM)372.3.9 SMM and VGA Access through GTT TLB372.3.10 ME Stolen Memory Accesses372.3.11 I/O Address Space382.3.11.1 PCI Express* I/O Address Mapping382.3.12 MCTP and KVM Flows392.3.13 Decode Rules and Cross-Bridge Address Mapping392.3.13.1 DMI Interface Decode Rules392.3.13.2 PCI Express* Interface Decode Rules422.3.13.3 Legacy VGA and I/O Range Decode Rules432.4 I/O Mapped Registers462.5 PCI Device 0 Function 0 Configuration Space Registers472.5.1 VID—Vendor Identification Register482.5.2 DID—Device Identification Register492.5.3 PCICMD—PCI Command Register492.5.4 PCISTS—PCI Status Register502.5.5 RID—Revision Identification Register522.5.6 CC—Class Code Register522.5.7 HDR—Header Type Register532.5.8 SVID—Subsystem Vendor Identification Register532.5.9 SID—Subsystem Identification Register532.5.10 CAPPTR—Capabilities Pointer Register542.5.11 PXPEPBAR—PCI Express* Egress Port Base Address Register542.5.12 MCHBAR—Host Memory Mapped Register Range Base Register552.5.13 GGC—GMCH Graphics Control Register552.5.14 DEVEN—Device Enable Register572.5.15 PAVPC—Protected Audio Video Path Control Register592.5.16 DPR—DMA Protected Range Register592.5.17 PCIEXBAR—PCI Express* Register Range Base Address Register602.5.18 DMIBAR—Root Complex Register Range Base Address Register622.5.19 MESEG_BASE—Intel® Management Engine Base Address Register632.5.20 MESEG_MASK—Intel® Management Engine Limit Address Register642.5.21 PAM0—Programmable Attribute Map 0 Register652.5.22 PAM1—Programmable Attribute Map 1 Register662.5.23 PAM2—Programmable Attribute Map 2 Register672.5.24 PAM3—Programmable Attribute Map 3 Register682.5.25 PAM4—Programmable Attribute Map 4 Register692.5.26 PAM5—Programmable Attribute Map 5 Register702.5.27 PAM6—Programmable Attribute Map 6 Register712.5.28 LAC—Legacy Access Control Register722.5.29 REMAPBASE—Remap Base Address Register762.5.30 REMAPLIMIT—Remap Limit Address Register772.5.31 TOM—Top of Memory Register772.5.32 TOUUD—Top of Upper Usable DRAM Register782.5.33 BDSM—Base Data of Stolen Memory Register792.5.34 BGSM—Base of GTT Stolen Memory Register792.5.35 TSEGMB—TSEG Memory Base Register802.5.36 TOLUD—Top of Low Usable DRAM Register802.5.37 SKPD—Scratchpad Data Register812.5.38 CAPID0_A—Capabilities A Register822.5.39 CAPID0_B—Capabilities B Register842.6 PCI Device 1 Function 0–2 Configuration Space Registers862.6.1 VID—Vendor Identification Register872.6.2 DID—Device Identification Register882.6.3 PCICMD—PCI Command Register882.6.4 PCISTS—PCI Status Register902.6.5 RID—Revision Identification Register922.6.6 CC—Class Code Register922.6.7 CL—Cache Line Size Register922.6.8 HDR—Header Type Register932.6.9 PBUSN—Primary Bus Number Register932.6.10 SBUSN—Secondary Bus Number Register932.6.11 SUBUSN—Subordinate Bus Number Register942.6.12 IOBASE—I/O Base Address Register952.6.13 IOLIMIT—I/O Limit Address Register952.6.14 SSTS—Secondary Status Register962.6.15 MBASE—Memory Base Address Register972.6.16 MLIMIT—Memory Limit Address Register982.6.17 PMBASE—Prefetchable Memory Base Address Register992.6.18 PMLIMIT—Prefetchable Memory Limit Address Register1002.6.19 PMBASEU—Prefetchable Memory Base Address Upper Register1002.6.20 PMLIMITU—Prefetchable Memory Limit Address Upper Register1012.6.21 CAPPTR—Capabilities Pointer Register1012.6.22 INTRLINE—Interrupt Line Register1022.6.23 INTRPIN—Interrupt Pin Register1022.6.24 BCTRL—Bridge Control Register1032.6.25 PM_CAPID—Power Management Capabilities Register1042.6.26 PM_CS—Power Management Control/Status Register1052.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register1072.6.28 SS—Subsystem ID and Subsystem Vendor ID Register1072.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register1082.6.30 MC—Message Control Register1092.6.31 MA—Message Address Register1102.6.32 MD—Message Data Register1102.6.33 PEG_CAPL—PCI Express-G Capability List Register1102.6.34 PEG_CAP—PCI Express-G Capabilities Register1112.6.35 DCAP—Device Capabilities Register1112.6.36 DCTL—Device Control Register1122.6.37 DSTS—Device Status Register1132.6.38 LCAP—Link Capabilities Register1142.6.39 LCTL—Link Control Register1162.6.40 LSTS—Link Status Register1182.6.41 SLOTCAP—Slot Capabilities Register1192.6.42 SLOTCTL—Slot Control Register1212.6.43 SLOTSTS—Slot Status Register1232.6.44 RCTL—Root Control Register1252.6.45 RSTS—Root Status Register1262.6.46 DCAP2—Device Capabilities 2 Register1272.6.47 DCTL2—Device Control 2 Register1282.6.48 LCAP2—Link Capabilities 2 Register1292.6.49 LCTL2—Link Control 2 Register1292.6.50 LSTS2—Link Status 2 Register1312.7 PCI Device 1 Function 0–2 Extended Configuration Registers1322.7.1 PVCCAP1—Port VC Capability Register 11332.7.2 PVCCAP2—Port VC Capability Register 21332.7.3 PVCCTL—Port VC Control Register1342.7.4 VC0RCAP—VC0 Resource Capability Register1352.7.5 VC0RCTL—VC0 Resource Control Register1362.7.6 VC0RSTS—VC0 Resource Status Register1372.7.7 PEG_TC—PCI Express* Completion Timeout Register1372.7.8 EQCTL0_1—Lane 0/1 Equalization Control Register1382.7.9 EQCTL2_3—Lane 2/3 Equalization Control Register1392.7.10 EQCTL4_5—Lane 4/5 Equalization Control Register1402.7.11 EQCTL6_7—Lane 6/7 Equalization Control Register1412.7.12 EQCTL8_9—Lane 8/9 Equalization Control Register1422.7.13 EQCTL10_11—Lane 10/11 Equalization Control Register1432.7.14 EQCTL12_13—Lane 12/13 Equalization Control Register1442.7.15 EQCTL14_15—Lane 14/15 Equalization Control Register1452.7.16 EQCFG—Equalization Configuration Register1462.8 PCI Device 2 Configuration Space Registers1482.8.1 VID2—Vendor Identification Register1492.8.2 DID2—Device Identification Register1492.8.3 PCICMD2—PCI Command Register1502.8.4 PCISTS2—PCI Status Register1512.8.5 RID2—Revision Identification Register1522.8.6 CC—Class Code Register1522.8.7 CLS—Cache Line Size Register1532.8.8 MLT2—Master Latency Timer Register1532.8.9 HDR2—Header Type Register1532.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register1542.8.11 GMADR—Graphics Memory Range Address Register1552.8.12 IOBAR—I/O Base Address Register1562.8.13 SVID2—Subsystem Vendor Identification Register1562.8.14 SID2—Subsystem Identification Register1572.8.15 ROMADR—Video BIOS ROM Base Address Register1572.8.16 CAPPOINT—Capabilities Pointer Register1572.8.17 INTRLINE—Interrupt Line Register1582.8.18 INTRPIN—Interrupt Pin Register1582.8.19 MINGNT—Minimum Grant Register1582.8.20 MAXLAT—Maximum Latency Register1592.8.21 MSAC—Multi Size Aperture Control Register1592.9 Device 2 IO Registers1602.9.1 Index—MMIO Address Register1602.9.2 Data—MMIO Data Register1602.10 PCI Device 6 Registers1612.10.1 VID—Vendor Identification Register1622.10.2 DID—Device Identification Register1632.10.3 PCICMD—PCI Command Register1632.10.4 PCISTS—PCI Status Register1662.10.5 RID—Revision Identification Register1672.10.6 CC—Class Code Register1682.10.7 CL—Cache Line Size Register1682.10.8 HDR—Header Type Register1682.10.9 PBUSN—Primary Bus Number Register1692.10.10 SBUSN—Secondary Bus Number Register1692.10.11 SUBUSN—Subordinate Bus Number Register1692.10.12 IOBASE—I/O Base Address Register1702.10.13 IOLIMIT—I/O Limit Address Register1702.10.14 SSTS—Secondary Status Register1712.10.15 MBASE—Memory Base Address Register1722.10.16 MLIMIT—Memory Limit Address Register1732.10.17 PMBASE—Prefetchable Memory Base Address Register1742.10.18 PMLIMIT—Prefetchable Memory Limit Address Register1752.10.19 PMBASEU—Prefetchable Memory Base Address Upper Register1762.10.20 PMLIMITU—Prefetchable Memory Limit Address Upper Register1772.10.21 CAPPTR—Capabilities Pointer Register1782.10.22 INTRLINE—Interrupt Line Register1782.10.23 INTRPIN—Interrupt Pin Register1792.10.24 BCTRL—Bridge Control Register1792.10.25 PM_CAPID—Power Management Capabilities Register1812.10.26 PM_CS—Power Management Control/Status Register1822.10.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register1842.10.28 SS—Subsystem ID and Subsystem Vendor ID Register1842.10.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register1852.10.30 MC—Message Control Register1852.10.31 MA—Message Address Register1862.10.32 MD—Message Data Register1872.10.33 PEG_CAPL—PCI Express-G Capability List Register1872.10.34 PEG_CAP—PCI Express-G Capabilities Register1882.10.35 DCAP—Device Capabilities Register1882.10.36 DCTL—Device Control Register1892.10.37 DSTS—Device Status Register1902.10.38 LCAP—Link Capabilities Register1912.10.39 LCTL—Link Control Register1932.10.40 LSTS—Link Status Register1952.10.41 SLOTCAP—Slot Capabilities Register1962.10.42 SLOTCTL—Slot Control Register1982.10.43 SLOTSTS—Slot Status Register2002.10.44 RCTL—Root Control Register2022.10.45 LCAP2—Link Capabilities 2 Register2022.11 PCI Device 6 Extended Configuration Registers2032.11.1 PVCCAP1—Port VC Capability Register 12042.11.2 PVCCAP2—Port VC Capability Register 22042.11.3 PVCCTL—Port VC Control Register2052.11.4 VC0RCAP—VC0 Resource Capability Register2052.11.5 VC0RCTL—VC0 Resource Control Register2072.11.6 VC0RSTS—VC0 Resource Status Register2082.11.7 RCLDECH—Root Complex Link Declaration Enhanced2082.11.8 ESD—Element Self Description Register2092.11.9 LE1D—Link Entry 1 Description Register2102.11.10 LE1A—Link Entry 1 Address Register2102.11.11 LE1AH—Link Entry 1 Address Register2112.11.12 APICBASE—APIC Base Address Register2112.11.13 APICLIMIT—APIC Base Address Limit Register2122.11.14 CMNRXERR—Common Rx Error Register2122.11.15 PEGTST—PCI Express* Test Modes Register2132.11.16 PEGUPDNCFG—PEG UPconfig/DNconfig Control Register2132.11.17 BGFCTL3—BGF Control 3 Register2142.11.18 EQPRESET1_2—Equalization Preset 1/2 Register2152.11.19 EQPRESET2_3_4—Equalization Preset 2/3/4 Register2152.11.20 EQPRESET6_7—Equalization Preset 6/7 Register2162.11.21 EQCFG—Equalization Configuration Register2162.12 Direct Media Interface Base Address Registers (DMIBAR)2172.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability Register2182.12.2 DMIPVCCAP1—DMI Port VC Capability Register 12192.12.3 DMIPVCCAP2—DMI Port VC Capability Register 22192.12.4 DMIPVCCTL—DMI Port VC Control Register2202.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Register2202.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register2212.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register2222.12.8 DMIVC1RCAP—DMI VC1 Resource Capability Register2222.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register2232.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register2242.12.11 DMIVCPRCAP—DMI VCp Resource Capability Register2242.12.12 DMIVCPRCTL—DMI VCp Resource Control Register2252.12.13 DMIVCPRSTS—DMI VCp Resource Status Register2262.12.14 DMIVCMRCAP—DMI VCm Resource Capability Register2262.12.15 DMIVCMRCTL—DMI VCm Resource Control Register2272.12.16 DMIVCMRSTS—DMI VCm Resource Status Register2282.12.17 DMIRCLDECH—DMI Root Complex Link Declaration Register2282.12.18 DMIESD—DMI Element Self Description Register2292.12.19 DMILE1D—DMI Link Entry 1 Description Register2302.12.20 DMILE1A—DMI Link Entry 1 Address Register2312.12.21 DMILUE1A—DMI Link Upper Entry 1 Address Register2312.12.22 DMILE2D—DMI Link Entry 2 Description Register2322.12.23 DMILE2A—DMI Link Entry 2 Address Register2332.12.24 LCAP—Link Capabilities Register2332.12.25 LCTL—Link Control Register2342.12.26 LSTS—DMI Link Status Register2352.12.27 LCTL2—Link Control 2 Register2362.12.28 LSTS2—Link Status 2 Register2382.13 MCHBAR Registers in Memory Controller—Channel 0 Registers2392.13.1 TC_DBP_C0—Timing of DDR – Bin Parameters Register2402.13.2 TC_RAP_C0—Timing of DDR – Regular Access Parameters Register2412.13.3 SC_IO_LATENCY_C0—IO Latency configuration Register2422.13.4 TC_SRFTP_C0–Self Refresh Timing Parameters Register2422.13.5 PM_PDWN_config_C0–Power-down Configuration Register2432.13.6 TC_RFP_C0—Refresh Parameters Register2442.13.7 TC_RFTP_C0—Refresh Timing Parameters Register2442.14 MCHBAR Registers in Memory Controller – Channel 12452.14.1 TC_DBP_C1—Timing of DDR – Bin Parameters Register2452.14.2 TC_RAP_C1—Timing of DDR – Regular Access Parameters Register2462.14.3 SC_IO_LATENCY_C1—IO Latency configuration Register2472.14.4 PM_PDWN_config_C1—Power-down Configuration Register2482.14.5 TC_RFP_C1—Refresh Parameters Register2492.14.6 TC_RFTP_C1—Refresh Timing Parameters Register2502.14.7 TC_SRFTP_C1—Self refresh Timing Parameters Register2502.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH)2512.15.1 CRDTCTL3—Credit Control 3 Register2512.15.2 CRDTCTL4—Credit Control 4 Register2522.16 MCHBAR Registers in Memory Controller – Common2532.16.1 MAD_CHNL—Address Decoder Channel Configuration Register2532.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register2542.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Register2552.16.4 PM_SREF_config—Self Refresh Configuration Register2562.17 Memory Controller MMIO Registers Broadcast Group Registers2572.17.1 PM_PDWN_config—Power-down Configuration Register2582.17.2 PM_CMD_PWR—Power Management Command Power Register2592.17.3 PM_BW_LIMIT_CONFIG—BW Limit Configuration Register2592.18 Integrated Graphics VTd Remapping Engine Registers2602.18.1 VER_REG—Version Register2612.18.2 CAP_REG—Capability Register2622.18.3 ECAP_REG—Extended Capability Register2662.18.4 GCMD_REG—Global Command Register2672.18.5 GSTS_REG—Global Status Register2712.18.6 RTADDR_REG—Root-Entry Table Address Register2722.18.7 CCMD_REG—Context Command Register2732.18.8 FSTS_REG—Fault Status Register2752.18.9 FECTL_REG—Fault Event Control Register2772.18.10 FEDATA_REG—Fault Event Data Register2782.18.11 FEADDR_REG—Fault Event Address Register2782.18.12 FEUADDR_REG—Fault Event Upper Address Register2782.18.13 AFLOG_REG—Advanced Fault Log Register2792.18.14 PMEN_REG—Protected Memory Enable Register2802.18.15 PLMBASE_REG—Protected Low-Memory Base Register2812.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register2822.18.17 PHMBASE_REG—Protected High-Memory Base Register2832.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register2842.18.19 IQH_REG—Invalidation Queue Head Register2852.18.20 IQT_REG—Invalidation Queue Tail Register2852.18.21 IQA_REG—Invalidation Queue Address Register2862.18.22 ICS_REG—Invalidation Completion Status Register2862.18.23 IECTL_REG—Invalidation Event Control Register2872.18.24 IEDATA_REG—Invalidation Event Data Register2882.18.25 IEADDR_REG—Invalidation Event Address Register2882.18.26 IEUADDR_REG—Invalidation Event Upper Address Register2892.18.27 IRTA_REG—Interrupt Remapping Table Address Register2892.18.28 IVA_REG—Invalidate Address Register2902.18.29 IOTLB_REG—IOTLB Invalidate Register2912.18.30 FRCDL_REG—Fault Recording Low Register2932.18.31 FRCDH_REG—Fault Recording High Register2942.18.32 VTPOLICY—DMA Remap Engine Policy Control Register2952.19 PCU MCHBAR Registers2962.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register2972.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration Register2982.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report Register2992.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report Register3002.19.5 MEM_TRML_INTERRUPT—Memory Thermal Interrupt Register3002.19.6 GT_PERF_STATUS—GT Performance Status Register3012.19.7 RP_STATE_LIMITS—RP-State Limitations Register3012.19.8 RP_STATE_CAP—RP State Capability Register3022.19.9 PCU_MMIO_FREQ_CLIPPING_CAUSE_STATUS Register3022.19.10 PCU_MMIO_FREQ_CLIPPING_CAUSE_LOG Register3042.19.11 SSKPD—Sticky Scratchpad Data Register3062.20 PXPEPBAR Registers3082.20.1 EPVC0RCTL—EP VC 0 Resource Control Register3082.21 Default PEG/DMI VTd Remapping Engine Registers3092.21.1 VER_REG—Version Register3102.21.2 CAP_REG—Capability Register3112.21.3 ECAP_REG—Extended Capability Register3152.21.4 GCMD_REG—Global Command Register3162.21.5 GSTS_REG—Global Status Register3202.21.6 RTADDR_REG—Root-Entry Table Address Register3212.21.7 CCMD_REG—Context Command Register3222.21.8 FSTS_REG—Fault Status Register3242.21.9 FECTL_REG—Fault Event Control Register3262.21.10 FEDATA_REG—Fault Event Data Register3272.21.11 FEADDR_REG—Fault Event Address Register3272.21.12 FEUADDR_REG—Fault Event Upper Address Register3272.21.13 AFLOG_REG—Advanced Fault Log Register3282.21.14 PMEN_REG—Protected Memory Enable Register3292.21.15 PLMBASE_REG—Protected Low-Memory Base Register3302.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register3312.21.17 PHMBASE_REG—Protected High-Memory Base Register3322.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register3332.21.19 IQH_REG—Invalidation Queue Head Register3342.21.20 IQT_REG—Invalidation Queue Tail Register3342.21.21 IQA_REG—Invalidation Queue Address Register3352.21.22 ICS_REG—Invalidation Completion Status Register3362.21.23 IECTL_REG—Invalidation Event Control Register3362.21.24 IEDATA_REG—Invalidation Event Data Register3372.21.25 IEADDR_REG—Invalidation Event Address Register3382.21.26 IEUADDR_REG—Invalidation Event Upper Address Register3382.21.27 IRTA_REG—Interrupt Remapping Table Address Register3392.21.28 IVA_REG—Invalidate Address Register3402.21.29 IOTLB_REG—IOTLB Invalidate Register341文件大小： 2.4 MB页数： 342Language: English打开用户手册
