Kingston Technology 8GB 667MHz DDR2 ECC Fully Buffered CL5 DIMM Dual Rank, x4 KVR667D2D4F5/8G 数据表
产品代码
KVR667D2D4F5/8G
continued
ValueRAM
Kingston.com
Document No. VALUERAM0607-001.A00 01/23/08 Page 3
Continued >>
DIMM Connector Pin Description:
Pin Name
Pin Description
Count
SCK
System Clock Input, positive line
1
1
SCK
System Clock Input, negative line
1
1
4
1
s
e
n
il
e
v
it
i
s
o
p
,
a
t
a
D
d
n
u
o
b
h
tr
o
N
y
r
a
m
ir
P
]
0
:
3
1
[
N
P
PN
PN
4
1
s
e
n
il
e
v
it
a
g
e
n
,
a
t
a
D
d
n
u
o
b
h
tr
o
N
y
r
a
m
ir
P
]
0
:
3
1
[
0
1
s
e
n
il
e
v
it
i
s
o
p
,
a
t
a
D
d
n
u
o
b
h
t
u
o
S
y
r
a
m
ir
P
]
0
:
9
[
S
P
PS
PS
0
1
s
e
n
il
e
v
it
a
g
e
n
,
a
t
a
D
d
n
u
o
b
h
t
u
o
S
y
r
a
m
ir
P
]
0
:
9
[
4
1
s
e
n
il
e
v
it
i
s
o
p
,
a
t
a
D
d
n
u
o
b
h
tr
o
N
y
r
a
d
n
o
c
e
S
]
0
:
3
1
[
N
S
SN
SN
4
1
s
e
n
il
e
v
it
a
g
e
n
,
a
t
a
D
d
n
u
o
b
h
tr
o
N
y
r
a
d
n
o
c
e
S
]
0
:
3
1
[
0
1
s
e
n
il
e
v
it
i
s
o
p
,
a
t
a
D
d
n
u
o
b
h
t
u
o
S
y
r
a
d
n
o
c
e
S
]
0
:
9
[
S
S
SS
SS
0
1
s
e
n
il
e
v
it
a
g
e
n
,
a
t
a
D
d
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o
b
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o
S
y
r
a
d
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o
c
e
S
]
0
:
9
[
1
t
u
p
n
I
k
c
o
l
C
)
D
P
S
(
t
c
e
t
e
D
e
c
n
e
s
e
r
P
l
a
ir
e
S
L
C
S
SDA
SPD Data Input / Output
1
3
B
M
A
e
h
t
n
i
r
e
b
m
u
n
M
M
I
D
e
h
t
t
c
e
l
e
s
o
t
d
e
s
u
o
s
l
a
,
s
t
u
p
n
I
s
s
e
r
d
d
A
D
P
S
]
0
:
2
[
A
S
VID[1:0]
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID[0] is V
VID[0] is V
DD
value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is V
CC
value: OPEN = 1.5 V, GND = 1.2 V
2
RESET
AMB reset signal
1
RFU
Reserved for Future Use
2
16
V
CC
8
)t
l
o
V
5
.
1
(
r
e
w
o
P
e
c
a
fr
e
t
n
I
l
e
n
n
a
h
C
B
M
A
d
n
a
r
e
w
o
P
e
r
o
C
B
M
A
V
DD
4
2
)t
l
o
V
8
.
1
(
r
e
w
o
P
O
/I
M
A
R
D
B
M
A
d
n
a
r
e
w
o
P
M
A
R
D
V
TT
DRAM Address/Command/Clock Termination Power (V
DD
/2)
4
V
DDSPD
SPD Power
1
V
SS
Ground
80
DNU/M_Test
The DNU/M_Test pin provides an external connection on R/Cs A-D for testing
the margin of Vref which is produced by a voltage divider on the module. It
is not intended to be used in normal system operation and must not be
connected (DNU) in a system. This test pin may have other features on future card designs
and if it does, will be included in this specification at that time.
1
the margin of Vref which is produced by a voltage divider on the module. It
is not intended to be used in normal system operation and must not be
connected (DNU) in a system. This test pin may have other features on future card designs
and if it does, will be included in this specification at that time.
1
1
Total
240
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency
2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
Absolute Maximum Ratings
0
95
°C
AMB device operating temperature (Ambient)
0
110
°C
Symbol
Parameter
MIN
MAX
Units
V
IN
, V
OUT
Voltage on any pin relative to V
SS
-0.3
1.75
V
V
CC
Voltage on V
CC
pin relative to V
SS
-0.3
1.75
V
V
DD
Voltage V
DD
pin relative to Vss
-0.5
2.3
V
V
TT
Voltage on V
TT
pin relative to V
SS
-0.5
2.3
V
T
STG
Storage temperature
-55
100
°C
T
CASE
DDR2 SDRAM device operating temperature (Ambient)
Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
95
(1)