Nxp Semiconductors LPC2194HBD64,151 ARM7 Microcontroller 16kB LQFP 64 LPC2194HBD64,151 数据表

LPC2194_4

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Match register updates are synchronized with pulse outputs to prevent generation of 
erroneous pulses. Software must ‘release’ new match values before they can become 
effective.

May be used as a standard timer if the PWM mode is not enabled.

A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output 
frequency is called f

osc

 and the ARM processor clock frequency is referred to as CCLK for 

purposes of rate equations, etc. f

osc

 and CCLK are the same value unless the PLL is 

running and connected. Refer to 

 for additional information.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input 
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled 
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the 
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper 
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so 
there is an additional divider in the loop to keep the CCO within its frequency range while 
the PLL is providing the desired output frequency. The output divider may be set to divide 
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, 
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and 
bypassed following a chip Reset and may be enabled by software. The program must 
configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a 
clock source. The PLL settling time is 100

µs.

Reset has two sources on the LPC2194: the RESET pin and Watchdog Reset. The 
RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip 
Reset by any source starts the Wake-up Timer (see Wake-up Timer description below), 
causing the internal chip reset to remain asserted until the external Reset is de-asserted, 
the oscillator is running, a fixed number of clocks have passed, and the on-chip flash 
controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which 
is the Reset vector. At that point, all of the processor and peripheral registers have been 
initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for 
chip operation are fully functional before the processor is allowed to execute instructions. 
This is important at power on, all types of Reset, and whenever any of the aforementioned 
functions are turned off for any reason. Since the oscillator and other functions are turned 
off during Power-down mode, any wake-up of the processor from Power-down mode 
makes use of the Wake-up Timer.