Nxp Semiconductors LPC2194HBD64,151 ARM7 Microcontroller 16kB LQFP 64 LPC2194HBD64,151 数据表

LPC2194_4

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

The PWM is based on the standard Timer block and inherits all of its features, although 
only the PWM function is pinned out on the LPC2194. The Timer is designed to count 
cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other 
actions when specified timer values occur, based on seven match registers. The PWM 
function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be 
used for more applications. For instance, multi-phase motor control typically requires 
three non-overlapping PWM outputs with individual control of all three pulse widths and 
positions.

Two match registers can be used to provide a single edge controlled PWM output. One 
match register (MR0) controls the PWM cycle rate, by resetting the count upon match. 
The other match register controls the PWM edge position. Additional single edge 
controlled PWM outputs require only one match register each, since the repetition rate is 
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a 
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled. 
Again, the MR0 match register controls the PWM cycle rate. The other match registers 
control the two PWM edge positions. Additional double edge controlled PWM outputs 
require only two match registers each, since the repetition rate is the same for all PWM 
outputs.

With double edge controlled PWM outputs, specific match registers control the rising and 
falling edge of the output. This allows both positive going PWM pulses (when the rising 
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling 
edge occurs prior to the rising edge).

Seven match registers allow up to six single edge controlled or three double edge 
controlled PWM outputs, or a mix of both types.

The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

Supports single edge controlled and/or double edge controlled PWM outputs. Single 
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the 
output is a constant LOW. Double edge controlled PWM outputs can have either edge 
occur at any position within a cycle. This allows for both positive going and negative 
going pulses.

Pulse period and width can be any number of timer counts. This allows complete 
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will 
occur at the same repetition rate.

Double edge controlled PWM outputs can be programmed to be either positive going 
or negative going pulses.