Texas Instruments LV32EVK01 Evaluation Kit LV32EVK01/NOPB LV32EVK01/NOPB 数据表
产品代码
LV32EVK01/NOPB
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer LVCMOS and LVDS Pinout by IDC Connector
The following two (2) tables illustrate how the serializer inputs are mapped to the IDC
connector J1, the LVDS outputs on the RJ-45 connector P1 pinout.
Note: Labels are also printed on the demo boards for both the LVCMOS input and
LVDS outputs.
J1 Pin No. Symbol
2
TxIN0
4
TxIN1
6
TxIN2
8
TxIN3
10
TxIN4
12
TxIN5
14
TxIN6
16
TxIN7
18
TxIN8
20
TxIN9
22
TxIN10
LVDS OUTPUT
24
TxIN11
P1 Pin No. Symbol
26
TxIN12
1
OUT 0 +
28
TxIN13
2
OUT 0 -
30
TxIN14
3
OUT 1 +
32
TxIN15
4
OUT 2 +
34
TxIN16
5
OUT 2 -
36
TxIN17
6
OUT 1 -
38
TxIN18
7
OUT 3 +
40
TxIN19
8
OUT 3 -
42
TxIN20
44
TxIN21
46
TxIN22
48
TxIN23
50
TxIN24
52
TxIN25
54
TxIN26
56
TxIN27
58
TxIN28
60
TxIN29
62
TxIN30
64
TxIN31
66
TxCLKIN
All Odd Pins GND
TTL INPUT
National Semiconductor Corporation
Date: 9/28/2009
Page 9 of 34
Page 9 of 34