Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 数据表
产品代码
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 3-2. C64x+ Cache Registers (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x0184 401C
L2IWC
L2 invalidate word count register
0x0184 4020
L1PIBAR
L1P invalidate base address register
0x0184 4024
L1PIWC
L1P invalidate word count register
0x0184 4030
L1DWIBAR
L1D writeback invalidate base address register
0x0184 4034
L1DWIWC
L1D writeback invalidate word count register
0x0184 4038
-
Reserved
0x0184 4040
L1DWBAR
L1D Block Writeback
0x0184 4044
L1DWWC
L1D Block Writeback
0x0184 4048
L1DIBAR
L1D invalidate base address register
0x0184 404C
L1DIWC
L1D invalidate word count register
0x0184 4050 - 0x0184 4FFF
-
Reserved
0x0184 5000
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2 writeback invalidate all register
0x0184 5008
L2INV
L2 Global Invalidate without writeback
0x0184 500C - 0x0184 5027
-
Reserved
0x0184 5028
L1PINV
L1P Global Invalidate
0x0184 502C - 0x0184 5039
-
Reserved
0x0184 5040
L1DWB
L1D Global Writeback
0x0184 5044
L1DWBINV
L1D Global Writeback with Invalidate
0x0184 5048
L1DINV
L1D Global Invalidate without writeback
0x0184 8000 - 0x0184 803C
MAR0 - MAR15
Reserved (corresponds to byte address 0x0000 0000 - 0x0FFF FFFF)
Memory Attribute Registers for ARM TCM (corresponds to byte address
0x0184 8040
MAR16
0x1000 0000 - 0x10FF FFFF)
0x0184 8044 - 0x0184 80FC
MAR17 - MAR63
Reserved (corresponds to byte address 0x1100 0000 - 0x3FFF FFFF)
0x0184 8100
MAR64
Reserved (corresponds to byte address 0x4000 0000 - 0x40FF FFFF)
0x0184 8104
MAR65
Reserved (corresponds to byte address 0x4100 0000 - 0x41FF FFFF)
Memory Attribute Registers for EMIFA (corresponds to byte address 0x4200
0x0184 8108 - 0x0184 8124
MAR66 - MAR73
0000 - 0x49FF FFFF)
0x0184 8128 - 0x0184 812C
MAR74 - MAR75
Reserved (corresponds to byte address 0x4A00 0000 - 0x4BFF FFFF)
Memory Attribute Registers for VLYNQ (corresponds to byte address
0x0184 8130 - 0x0184 813C
MAR76 - MAR79
0x4C00 0000 - 0x4FFF FFFF)
0x0184 8140 - 0x0184 81FC
MAR80 - MAR127
Reserved (corresponds to byte address 0x5000 0000 - 0x7FFF FFFF)
Memory Attribute Registers for DDR2 (corresponds to byte address 0x8000
0x0184 8200 - 0x0184 82FC
MAR128 - MAR191
0000 - 0xBFFF FFFF)
0x0184 8300 - 0x0184 83FC
MAR192 - MAR255
Reserved (corresponds to byte address 0xC000 0000 - 0xFFFF FFFF)
3.4.3
Peripherals
The DSP has access/controllability of the following peripherals:
•
HDVICP0/1
•
EDMA
•
McASP0/1
•
2 Timers (Timer0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers
3.4.4
DSP Interrupt Controller
The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s
available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts
section. For more detailed on the DSP Interrupt Controller, see the TMS320C64x+ DSP Megamodule
Reference Guide (literature number
available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts
section. For more detailed on the DSP Interrupt Controller, see the TMS320C64x+ DSP Megamodule
Reference Guide (literature number
18
Device Overview
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