数据表 (TMDXEVM6467T)目录1 Digital Media System-on-Chip (DMSoC)11.1 Features11.2 Description31.3 Functional Block Diagram5Table of Contents62 Revision History73 Device Overview83.1 Device Characteristics83.2 Device Compatibility103.3 ARM Subsystem103.3.1 ARM926EJ-S RISC CPU103.3.2 CP15113.3.3 MMU113.3.4 Caches and Write Buffer113.3.5 Tightly Coupled Memory (TCM)123.3.6 Advanced High-Performance Bus (AHB)123.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)123.3.8 ARM Memory Mapping123.3.8.1 ARM Internal Memories123.3.8.2 External Memories123.3.8.3 DSP Memories133.3.8.4 ARM-DSP Integration133.3.9 Peripherals133.3.10 PLL Controller (PLLC)133.3.11 Power and Sleep Controller (PSC)133.3.12 ARM Interrupt Controller (AINTC)133.3.13 System Module143.3.14 Power Management143.4 DSP Subsystem143.4.1 C64x+ DSP CPU Description143.4.2 DSP Memory Mapping173.4.2.1 ARM Internal Memories173.4.2.2 External Memories173.4.2.3 DSP Internal Memories173.4.2.4 C64x+ CPU173.4.3 Peripherals183.4.4 DSP Interrupt Controller183.5 Memory Map Summary193.6 Pin Assignments233.6.1 Pin Map (Bottom View)233.7 Terminal Functions303.8 Device Support783.8.1 Development Support783.8.2 Device and Development-Support Tool Nomenclature783.9 Documentation Support803.9.1 Related Documentation From Texas Instruments803.10 Community Resources804 Device Configurations814.1 System Module Registers814.2 Power Considerations834.3 Clock Considerations864.3.1 Clock Configurations after Device Reset864.3.1.1 Device Clock Frequency864.3.1.2 Module Clock State864.3.2 Clock Control884.3.2.1 Video Clock Control Register884.3.2.2 TSIF Control894.3.2.3 Video and TSIF Clock Disable904.3.3 Clock and Oscillator Control914.4 Boot Sequence934.4.1 Boot Modes934.4.2 Boot Mode Registers934.4.2.1 DSPBOOTADDR Register934.4.2.2 BOOTSTAT Register944.4.2.3 BOOTCFG Register954.4.2.4 ARMBOOT Register974.4.2.5 ARMWAIT Register974.5 Configurations At Reset994.5.1 Device and Peripheral Configurations at Device Reset994.5.2 EMIFA CS2 Bus Width (CS2BW)1004.5.3 PCI Enable (PCIEN)1004.5.4 DSPBOOT1014.6 Configurations After Reset1024.6.1 Switch Central Resource (SCR) Bus Priorities1024.6.2 Peripheral Selection After Device Reset1054.6.2.1 HPICTL Register1064.6.2.2 USBCTL Register1064.6.2.3 PWMCTL (Trigger Source) Control Register1084.6.2.4 EDMATCCFG Register1094.7 Multiplexed Pin Configurations1104.7.1 Pin Muxing Selection At Reset1104.7.2 Pin Muxing Selection After Reset1104.7.2.1 PINMUX0 Register Description1104.7.2.2 PINMUX1 Register Description1124.7.3 Pin Multiplexing Details1134.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing1134.7.3.2 PWM Signal Muxing1154.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)1164.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)1174.7.3.5 TSIF1 Input Signal Muxing (Serial Only)1184.7.3.6 TSIF1 Output Signal Muxing (Serial Only)1194.7.3.7 CRGEN Signal Muxing1204.7.3.8 UART0 Pin Muxing1214.7.3.9 UART1 Pin Muxing1234.7.3.10 UART2 Pin Muxing1244.7.3.11 ARM/DSP Communications Interrupts1264.7.3.12 Emulation Control1304.8 Debugging Considerations1324.8.1 Pullup/Pulldown Resistors1325 System Interconnect1346 Device Operating Conditions1356.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)1356.2 Recommended Operating Conditions1366.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)1377 Peripheral Information and Electrical Specifications1397.1 Parameter Information1397.1.1 1.8-V and 3.3-V Signal Transition Levels1397.1.2 3.3-V Signal Transition Rates1397.1.3 Timing Parameters and Board Routing Analysis1407.2 Recommended Clock and Control Signal Transition Behavior1407.3 Power Supplies1417.3.1 Power-Supply Sequencing1417.3.2 Power-Supply Design Considerations1417.3.3 Power-Supply Decoupling1417.3.4 DM6467T Power and Clock Domains1417.3.5 Power and Sleep Controller (PSC)1457.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins1497.4.1 Clock Input Option 1—Crystal1497.4.1.1 33.3-MHz for System Oscillator Clock Input Option 1—Crystal1497.4.1.2 24-MHz Auxiliary Oscillator Clock Input Option 1—Crystal1507.4.2 Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input1527.4.2.1 33.3-MHz System Oscillator Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input1527.4.2.2 24-MHz Auxiliary Oscillator Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input1527.5 Clock PLLs1537.5.1 PLL1 and PLL21537.5.2 PLL Controller Register Description(s)1567.5.3 Clock PLL Considerations With External Clock Sources1577.5.4 Output Clocks (CLKOUT0, AUDIO_CLK1, AUDIO_CLK0) - Clock Select Logic1577.5.5 Clock PLL Electrical Data/Timing (Input and Output Clocks)1597.6 Enhanced Direct Memory Access (EDMA3) Controller1627.6.1 EDMA3 Channel Synchronization Events1627.6.2 EDMA Peripheral Register Description(s)1657.7 Reset1827.7.1 Power-on Reset (POR Pin)1827.7.1.1 Usage of POR versus RESET Pins1837.7.1.2 Latching Boot and Configuration Pins1837.7.2 Warm Reset (RESET Pin)1837.7.3 Maximum Reset1847.7.4 System Reset1847.7.5 C64x+ Local Reset (DSP Local Reset)1857.7.6 Peripheral Local Reset1857.7.7 Reset Priority1857.7.7.1 Reset Type Status (RSTYPE) Register1867.7.8 Pin Behaviors at Reset1867.7.9 Reset Electrical Data/Timing1907.8 Interrupts1937.8.1 ARM CPU Interrupts1937.8.2 DSP Interrupts1967.9 External Memory Interface (EMIF)1997.9.1 Asynchronous EMIF (EMIFA)1997.9.2 NAND (NAND, SmartMedia/SSFDC, xD)1997.9.3 EMIFA Peripheral Register Description(s)1997.9.4 EMIFA Electrical Data/Timing2017.10 DDR2 Memory Controller2067.10.1 DDR2 Memory Controller Electrical Data/Timing2077.10.2 DDR2 Interface2077.10.2.1 DDR2 Interface Schematic2077.10.2.2 Compatible JEDEC DDR2 Devices2077.10.2.3 PCB Stackup2087.10.2.4 Placement2117.10.2.5 DDR2 Keep Out Region2127.10.2.6 Bulk Bypass Capacitors2137.10.2.7 High-Speed Bypass Capacitors2137.10.2.8 Net Classes2137.10.2.9 DDR2 Signal Termination2147.10.2.10 VREF Routing2157.10.2.11 DDR2 CK and ADDR_CTRL Routing2157.11 Video Port Interface (VPIF)2197.11.1 VPIF Bus Master Memory Map2197.11.2 VPIF Clock Control (Capture and Display)2197.11.3 VPIF Register Descriptions2227.11.4 VPIF Electrical Data/Timing2257.12 Transport Stream Interface (TSIF)2277.12.1 TSIF Bus Master2277.12.2 TSIF Clock Control2287.12.3 TSIF Peripheral Register Description(s)2307.12.4 Transport Stream Interface (TSIF) Electrical Data/Timing2357.13 Clock Recovery Generator (CRGEN)2377.13.1 CRGEN Peripheral Register Description(s)2377.13.2 CRGEN Electrical Data/Timing2397.14 Video Data Conversion Engine (VDCE)2407.14.1 VDCE Bus Master2407.14.2 VDCE Register Description(s)2417.15 Peripheral Component Interconnect (PCI)2437.15.1 PCI Device-Specific Information2437.15.2 PCI External Master Memory Map2447.15.3 PCI Peripheral Register Description(s)2457.15.4 PCI Electrical Data/Timing2487.16 Ethernet MAC (EMAC)2497.16.1 EMAC Device-Specific Information2497.16.2 EMAC Bus Master Memory Map2507.16.3 EMAC Peripheral Register Description(s)2517.16.4 EMAC Electrical Data/Timing2557.17 Management Data Input/Output (MDIO)2597.17.1 MDIO Peripheral Register Description(s)2597.17.2 Management Data Input/Output (MDIO) Electrical Data/Timing2607.18 Host-Port Interface (HPI) Peripheral2617.18.1 HPI Device-Specific Information2617.18.2 HPI Bus Master2617.18.3 HPI Peripheral Register Description(s)2627.18.4 HPI Electrical Data/Timing2637.19 USB 2.0 [see Note]2697.19.1 USB DMA Master2697.19.2 USB2.0 Device-Specific Information2707.19.3 USB2.0 Peripheral Register Description(s)2717.19.4 USB2.0 Electrical Data/Timing2787.20 ATA Controller2797.20.1 ATA Bus Master Memory Map2797.20.2 ATA Peripheral Register Description(s)2807.20.3 ATA Electrical Data/Timing2817.20.3.1 ATA PIO Data Transfer AC Timing2817.20.3.2 ATA Multiword DMA Timing2837.20.3.3 ATA Ultra DMA Timing2857.20.3.4 ATA HDDIR Timing2927.21 VLYNQ2947.21.1 VLYNQ Bus Master Memory Map2947.21.2 VLYNQ Peripheral Register Description(s)2957.21.3 VLYNQ Electrical Data/Timing2977.22 Multichannel Audio Serial Port (McASP0/1) Peripherals2997.22.1 McASP Device-Specific Information2997.22.2 McASP0 and McASP1 Peripheral Register Description(s)3007.22.3 McASP0 and McASP1 Electrical Data/Timing3057.22.3.1 Multichannel Audio Serial Port (McASP0) Timing3057.22.3.2 Multichannel Audio Serial Port (McASP1) DIT Timing3097.23 Serial Peripheral Interface (SPI)3117.23.1 SPI Device-Specific Information3117.23.2 SPI Peripheral Register Description(s)3117.23.3 SPI Electrical Data/Timing3127.24 Universal Asynchronouse Receiver/Transmitter (UART)3267.24.1 UART Device-Specific Information3267.24.2 UART Peripheral Register Description(s)3277.24.3 UART Electrical Data/Timing [Receive/Transmit]3317.24.4 IrDA Interface Receive/Transmit Timings3327.25 Inter-Integrated Circuit (I2C)3337.25.1 I2C Peripheral Register Description(s)3347.25.2 I2C Electrical Data/Timing3357.26 Pulse Width Modulator (PWM)3377.26.1 PWM Device-Specific Information3377.26.2 PWM Peripheral Register Description(s)3377.26.3 PWM0/1 Electrical Data/Timing3387.27 Timers3397.27.1 Timers Device-Specific Information3397.27.2 Timer Peripheral Register Description(s)3397.27.3 Timer Electrical Data/Timing3417.28 General-Purpose Input/Output (GPIO)3427.28.1 GPIO Device-Specific Information3427.28.2 GPIO Peripheral Register Description(s)3437.28.3 GPIO Peripheral Input/Output Electrical Data/Timing3447.29 IEEE 1149.1 JTAG3457.29.1 JTAG ID (JTAGID) Register Description(s)3457.29.2 JTAG Test-Port Electrical Data/Timing3468 Mechanical Packaging and Orderable Information3488.1 Thermal Data for CUT3488.2 Packaging Information348文件大小: 2.1 MB页数: 352Language: English打开用户手册